| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 110 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
112 if (!isAllocated(Regs[i]))
137 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
138 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
143 unsigned Reg = Regs[FirstUnalloc];
149 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
151 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
156 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 180 void setUsed(BitVector &Regs) {
181 RegsAvailable.reset(Regs);
183 void setUnused(BitVector &Regs) {
184 RegsAvailable |= Regs;
|
| CallingConvLower.h | 281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
283 if (!isAllocated(Regs[i]))
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
309 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
314 unsigned Reg = Regs[FirstUnalloc];
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs,
322 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
327 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
361 // Returns count of byval in-regs arguments proceed.
|
| RegisterPressure.h | 226 void addLiveRegs(ArrayRef<unsigned> Regs);
342 void increaseRegPressure(ArrayRef<unsigned> Regs);
343 void decreaseRegPressure(ArrayRef<unsigned> Regs);
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
171 const CodeGenRegister::Set &Regs = RC.getMembers();
172 if (Regs.empty())
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
315 const std::vector<CodeGenRegister*> &Regs,
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 Record *Reg = Regs[i]->TheDef;
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace")
[all...] |
| CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs):
160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
349 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| CodeGenTarget.cpp | 217 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
218 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
219 if (I == Regs.end())
|
| CodeGenRegisters.h | 670 // Compute the set of registers completely covered by the registers in Regs.
671 // The returned BitVector will have a bit set for each register in Regs,
673 // registers in Regs.
677 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
| AsmMatcherEmitter.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 51 const unsigned *Regs,
55 RegNo = Regs[RegNo];
186 const unsigned *Regs) {
190 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
196 const unsigned *Regs) {
200 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
206 const unsigned *Regs) {
211 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
213 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
218 const unsigned *Regs) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterPressure.cpp | 116 void RegPressureTracker::increaseRegPressure(ArrayRef<unsigned> Regs) {
117 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
118 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
119 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
126 TRI->getRegUnitPressureSets(Regs[I]),
127 TRI->getRegUnitWeight(Regs[I]));
133 void RegPressureTracker::decreaseRegPressure(ArrayRef<unsigned> Regs) {
134 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
135 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
136 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I])
[all...] |
| ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs;
586 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
600 while (!Regs.empty()) {
602 dv = Regs.pop_back_val().Value;
609 DomainValue *Latest = Regs.pop_back_val().Value;
|
| AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
|
| AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs,
75 Regs.push_back(Reg);
154 // Examine the live-in regs of all successors.
537 std::vector<unsigned> Regs;
538 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
539 assert(Regs.size() > 0 && "Empty register group!");
540 if (Regs.size() == 0)
550 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
551 unsigned Reg = Regs[i];
555 // If Reg has any references, then collect possible rename regs
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 310 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
315 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
319 const unsigned *Regs, RegisterKind RegKind);
323 const unsigned *Regs, RegisterKind RegKind,
468 // Parse a register of group Group. If Regs is nonnull, use it to map
473 const unsigned *Regs, bool IsAddress) {
478 if (Regs && Regs[Reg.Num] == 0)
482 if (Regs)
483 Reg.Num = Regs[Reg.Num]
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 592 SmallVector<std::pair<unsigned,bool>, 4> Regs;
624 Regs.push_back(std::make_pair(Reg, isKill));
627 if (Regs.empty())
629 if (Regs.size() > 1 || StrOpc== 0) {
633 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
634 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
635 } else if (Regs.size() == 1) {
638 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
[all...] |
| ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs,
279 /// registers in Regs as the register operands that would be loaded / stored.
287 ArrayRef<std::pair<unsigned, bool> > Regs,
290 unsigned NumRegs = Regs.size();
320 NewBase = Regs[NumRegs-1].first;
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
354 | getKillRegState(Regs[i].second));
393 SmallVector<std::pair<unsigned, bool>, 8> Regs;
400 Regs.push_back(std::make_pair(Reg, isKill));
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)
[all...] |
| Thumb2SizeReduction.cpp | 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
215 if (*Regs == ARM::CPSR)
648 // Early exit if the regs aren't all low regs.
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 826 SmallPtrSet<const SCEV *, 16> &Regs,
839 SmallPtrSet<const SCEV *, 16> &Regs,
843 SmallPtrSet<const SCEV *, 16> &Regs,
853 SmallPtrSet<const SCEV *, 16> &Regs,
875 if (!Regs.count(AR->getOperand(1))) {
876 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
899 /// that refers to one of those regs an instant loser.
901 SmallPtrSet<const SCEV *, 16> &Regs,
909 if (Regs.insert(Reg)) {
910 RateRegister(Reg, Regs, L, SE, DT)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 248 SmallVector<SDValue, 4> Regs;
249 Regs.push_back(Val);
253 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
259 Regs.push_back(DAG.getUNDEF(VT));
262 Regs.data(), Regs.size()));
[all...] |
| R600InstrInfo.cpp | 1007 std::vector<unsigned> Regs;
1013 return Regs;
1018 Regs.push_back(SuperReg);
1021 Regs.push_back(Reg);
1024 return Regs;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 602 /// Regs - This list holds the registers assigned to the values.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
623 Regs.push_back(Reg + i);
643 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
700 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
