| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
58 SUBREG_TO_REG = 9,
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
83 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
109 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
209 case TargetOpcode::SUBREG_TO_REG:
|
| PeepholeOptimizer.cpp | 213 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
220 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
222 // The problem here is that SUBREG_TO_REG is there to assert that an
226 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 654 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
692 case TargetOpcode::SUBREG_TO_REG:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 266 case TargetOpcode::SUBREG_TO_REG:
306 case TargetOpcode::SUBREG_TO_REG:
|
| InstrEmitter.cpp | 512 Opc == TargetOpcode::SUBREG_TO_REG) {
539 // Create the insert_subreg or subreg_to_reg machine instruction.
543 // If creating a subreg_to_reg, then the first input operand
545 if (Opc == TargetOpcode::SUBREG_TO_REG) {
557 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
702 Opc == TargetOpcode::SUBREG_TO_REG) {
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 55 case TargetOpcode::SUBREG_TO_REG:
107 case TargetOpcode::SUBREG_TO_REG:
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 232 ResNode = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
