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    Searched refs:basereg (Results 1 - 3 of 3) sorted by null

/external/pixman/pixman/
pixman-arm-neon-asm.h	112 .macro pixldst numbytes, op, elem_size, basereg, mem_operand, abits variable 114 pixldst4 op, elem_size, %(basereg+4), %(basereg+5), \ variable 115 %(basereg+6), %(basereg+7), mem_operand, abits variable 117 pixldst2 op, elem_size, %(basereg+2), %(basereg+3), mem_operand, abits variable 119 pixldst1 op, elem_size, %(basereg+1), mem_operand, abits variable 122 pixldst0 op, 32, %(basereg+0), 1, mem_operand, abits variable 124 pixldst0 op, 16, %(basereg+0), 2, mem_operand, abit variable 125 pixldst0 op, 16, %(basereg+0), 3, mem_operand, abits variable 127 pixldst0 op, 8, %(basereg+0), 4, mem_operand, abits variable 128 pixldst0 op, 8, %(basereg+0), 5, mem_operand, abits variable 129 pixldst0 op, 8, %(basereg+0), 6, mem_operand, abits variable 130 pixldst0 op, 8, %(basereg+0), 7, mem_operand, abits variable 134 pixldst0 op, 16, %(basereg+0), 1, mem_operand, abits variable 136 pixldst0 op, 8, %(basereg+0), 2, mem_operand, abits variable 137 pixldst0 op, 8, %(basereg+0), 3, mem_operand, abits variable 140 pixldst0 op, 8, %(basereg+0), 1, mem_operand, abits variable 146 .macro pixld numpix, bpp, basereg, mem_operand, abits=0 variable 149 pixldst4 vld4, 8, %(basereg+4), %(basereg+5), \\ variable 150 %(basereg+6), %(basereg+7), mem_operand, abits variable 152 pixldst3 vld3, 8, %(basereg+3), %(basereg+4), %(basereg+5), mem_operand variable 154 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 4, mem_operand variable 155 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 5, mem_operand variable 156 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 6, mem_operand variable 157 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 7, mem_operand variable 159 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 2, mem_operand variable 160 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 3, mem_operand variable 162 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 1, mem_operand variable 169 .macro pixst numpix, bpp, basereg, mem_operand, abits=0 variable 172 pixldst4 vst4, 8, %(basereg+4), %(basereg+5), \\ variable 173 %(basereg+6), %(basereg+7), mem_operand, abits variable 175 pixldst3 vst3, 8, %(basereg+3), %(basereg+4), %(basereg+5), mem_operand variable 177 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 4, mem_operand variable 178 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 5, mem_operand variable 179 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 6, mem_operand variable 180 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 7, mem_operand variable 182 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 2, mem_operand variable 183 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 3, mem_operand variable 185 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 1, mem_operand variable 192 .macro pixld_a numpix, bpp, basereg, mem_operand variable 194 pixld numpix, bpp, basereg, mem_operand, %(bpp * numpix) variable 196 pixld numpix, bpp, basereg, mem_operand, 128 variable 200 .macro pixst_a numpix, bpp, basereg, mem_operand variable 202 pixst numpix, bpp, basereg, mem_operand, %(bpp * numpix) variable 204 pixst numpix, bpp, basereg, mem_operand, 128 variable 298 .macro pixld_s_internal numbytes, elem_size, basereg, mem_operand variable 300 pixld2_s elem_size, %(basereg+4), %(basereg+5), mem_operand variable 301 pixld2_s elem_size, %(basereg+6), %(basereg+7), mem_operand variable 304 pixld2_s elem_size, %(basereg+2), %(basereg+3), mem_operand variable 306 pixld1_s elem_size, %(basereg+1), mem_operand variable 309 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable 311 pixld0_s elem_size, %(basereg+0), 2, mem_operand variable 312 pixld0_s elem_size, %(basereg+0), 3, mem_operand variable 314 pixld0_s elem_size, %(basereg+0), 4, mem_operand variable 315 pixld0_s elem_size, %(basereg+0), 5, mem_operand variable 316 pixld0_s elem_size, %(basereg+0), 6, mem_operand variable 317 pixld0_s elem_size, %(basereg+0), 7, mem_operand variable 321 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable 323 pixld0_s elem_size, %(basereg+0), 2, mem_operand variable 324 pixld0_s elem_size, %(basereg+0), 3, mem_operand variable 327 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable 333 .macro pixld_s numpix, bpp, basereg, mem_operand variable     [all...]
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/
x86expr.c	672 int basereg = REG3264_NONE; /* "base" register (for SIB) */ local 723 /* Find a basereg (*1, but not indexreg), if there is one. 734 basereg == REG3264_NONE) 735 basereg = i; 742 * Also check basereg (must be a GPR if present) and indexreg 745 if (basereg >= SIMDREGS && 747 int temp = basereg; 748 basereg = indexreg; 751 if (basereg >= REG64_RIP || indexreg < SIMDREGS) { 756 } else if (indexreg != REG3264_NONE && basereg == REG3264_NONE     [all...]
/external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp	204 unsigned BaseReg, IndexReg, TmpReg, Scale; 213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), 217 unsigned getBaseReg() { return BaseReg; } 246 // If we already have a BaseReg, then assume this is the IndexReg with 248 if (!BaseReg) { 249 BaseReg = TmpReg; 251 assert (!IndexReg && "BaseReg/IndexReg already set!"); 282 // If we already have a BaseReg, then assume this is the IndexReg with 284 if (!BaseReg) { 285 BaseReg = TmpReg 1010 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local 1020 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local     [all...]

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