| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 313 unsigned NumDefs = MI->getDesc().getNumDefs();
343 NumDefs = DefMI->getDesc().getNumDefs();
422 if (MCID.getNumDefs() != 1)
444 if (MCID.getNumDefs() != 1)
|
| ExecutionDepsFix.cpp | 457 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
511 for (unsigned i = mi->getDesc().getNumDefs(),
521 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
540 for (unsigned i = mi->getDesc().getNumDefs(),
|
| TargetInstrInfo.cpp | 121 bool HasDef = MCID.getNumDefs();
190 SrcOpIdx1 = MCID.getNumDefs();
|
| MachineCSE.cpp | 514 unsigned NumDefs = MI->getDesc().getNumDefs() +
|
| MachineLICM.cpp | [all...] |
| MachineVerifier.cpp | 814 if (MONum < MCID.getNumDefs()) {
868 if (MONum < MCID.getNumDefs()) {
[all...] |
| RegAllocFast.cpp | [all...] |
| RegisterCoalescer.cpp | 766 if (MCID.getNumDefs() != 1)
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 134 if (i+II.getNumDefs() < II.getNumOperands()) {
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
214 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
727 countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses);
728 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
751 bool HasOptPRefs = II.getNumDefs() > NumResults;
754 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
756 AddOperand(MIB, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
787 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
788 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
[all...] |
| FastISel.cpp | [all...] |
| ScheduleDAGSDNodes.cpp | 124 if (ResNo >= II.getNumDefs() &&
125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
453 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
544 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
631 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| ResourcePriorityQueue.cpp | 559 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs());
|
| ScheduleDAGFast.cpp | 437 unsigned NumRes = MCID.getNumDefs();
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 179 unsigned getNumDefs() const {
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 791 unsigned NumDefs = Desc->getNumDefs();
798 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
805 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 309 if (II.getNumDefs() >= 1) {
329 if (II.getNumDefs() >= 1) {
352 if (II.getNumDefs() >= 1) {
376 if (II.getNumDefs() >= 1) {
398 if (II.getNumDefs() >= 1) {
421 if (II.getNumDefs() >= 1) {
444 if (II.getNumDefs() >= 1) {
463 if (II.getNumDefs() >= 1) {
[all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | [all...] |
