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  /external/llvm/lib/CodeGen/
AllocationOrder.cpp 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
RegAllocBase.cpp 101 << MRI->getRegClass(VirtReg->reg)->getName()
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
PeepholeOptimizer.cpp 164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
269 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
363 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
VirtRegMap.cpp 102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
123 << MRI->getRegClass(Reg)->getName() << "\n";
131 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
TargetRegisterInfo.cpp 89 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
158 return TRI->getRegClass(I + countTrailingZeros(Common));
MachineSink.cpp 135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
506 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
OptimizePHIs.cpp 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
Spiller.cpp 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
TargetInstrInfo.cpp 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
54 return TRI->getRegClass(RegClass);
326 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
331 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
RegisterPressure.cpp 52 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
68 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
119 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
136 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
331 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
LiveRangeEdit.cpp 34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
399 << MRI.getRegClass(LI.reg)->getName() << '\n');
MachineRegisterInfo.cpp 52 const TargetRegisterClass *OldRC = getRegClass(Reg);
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
RegisterCoalescer.cpp 284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
287 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
293 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
651 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
774 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
824 RCForInst = TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), DefRC,
    [all...]
CalcSpillWeights.cpp 82 const TargetRegisterClass *rc = mri.getRegClass(reg);
TailDuplication.cpp 285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
394 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
431 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
441 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
    [all...]
UnreachableBlockElim.cpp 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
  /external/llvm/lib/Target/R600/
SIFixSGPRCopies.cpp 117 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
AMDGPUInstrInfo.cpp 237 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
  /external/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
283 MRI->getRegClass(MI->getOperand(1).getReg());
284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
541 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
557 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
563 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
161 DstRC = MRI->getRegClass(VRBase);
220 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
238 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
319 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
426 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
485 TRC == MRI->getRegClass(SrcReg)) {
536 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
577 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
594 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx)
    [all...]
  /external/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.cpp 36 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
37 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
  /external/llvm/utils/TableGen/
CodeGenTarget.h 125 return *getRegBank().getRegClass(R);
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUInstrInfo.cpp 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);

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