HomeSort by relevance Sort by last modified time
    Searched refs:reg1 (Results 1 - 25 of 80) sorted by null

1 2 3 4

  /external/llvm/test/MC/MachO/
bad-macro.s 5 .macro test_macro reg1, reg2
  /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/
x86gas.pl 70 { my($addr,$reg1,$reg2,$idx)=@_;
77 $reg1 = "%$reg1" if ($reg1);
84 $ret .= "($reg1,$reg2,$idx)";
86 elsif ($reg1)
87 { $ret .= "($reg1)"; }
x86nasm.pl 36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
60 $ret .= "+$reg1" if ($reg1 ne "");
63 { $ret .= "$reg1"; }
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
59 $ret .= "+$reg1" if ($reg1 ne "");
62 { $ret .= "$reg1"; }
  /external/openssl/crypto/perlasm/
x86gas.pl 70 { my($addr,$reg1,$reg2,$idx)=@_;
77 $reg1 = "%$reg1" if ($reg1);
84 $ret .= "($reg1,$reg2,$idx)";
86 elsif ($reg1)
87 { $ret .= "($reg1)"; }
x86nasm.pl 36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
60 $ret .= "+$reg1" if ($reg1 ne "");
63 { $ret .= "$reg1"; }
x86masm.pl 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
59 $ret .= "+$reg1" if ($reg1 ne "");
62 { $ret .= "$reg1"; }
  /external/pixman/pixman/
pixman-arm-simd-asm.S 223 .macro src_0565_8888_2pixels, reg1, reg2
224 and SCRATCH, WK&reg1, MASK @ 00000GGGGGG0000000000gggggg00000
225 bic WK&reg2, WK&reg1, MASK @ RRRRR000000BBBBBrrrrr000000bbbbb
227 mov WK&reg1, WK&reg2, lsl #16 @ rrrrr000000bbbbb0000000000000000
229 bic WK&reg2, WK&reg2, WK&reg1, lsr #16 @ RRRRR000000BBBBB0000000000000000
230 orr WK&reg1, WK&reg1, WK&reg1, lsr #5 @ rrrrrrrrrr0bbbbbbbbbb00000000000
232 pkhtb WK&reg1, WK&reg1, WK&reg1, asr #5 @ rrrrrrrr--------bbbbbbbb-------
    [all...]
pixman-arm-neon-asm.h 76 .macro pixldst1 op, elem_size, reg1, mem_operand, abits variable
78 op&.&elem_size {d&reg1}, [&mem_operand&, :&abits&]!
80 op&.&elem_size {d&reg1}, [&mem_operand&]!
84 .macro pixldst2 op, elem_size, reg1, reg2, mem_operand, abits variable
86 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&, :&abits&]! variable
88 op&.&elem_size {d&reg1, d&reg2}, [&mem_operand&]! variable
92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]! variable
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]! variable
100 .macro pixldst0 op, elem_size, reg1, idx, mem_operand, abit variable
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]! variable
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]! variable
212 .macro pixld1_s elem_size, reg1, mem_operand variable
256 .macro pixld2_s elem_size, reg1, reg2, mem_operand variable
275 pixld1_s elem_size, reg1, mem_operand variable
280 .macro pixld0_s elem_size, reg1, idx, mem_operand variable
    [all...]
pixman-region.c 295 PREFIX (_equal) (region_type_t *reg1, region_type_t *reg2)
301 if (reg1->extents.x1 != reg2->extents.x1)
304 if (reg1->extents.x2 != reg2->extents.x2)
307 if (reg1->extents.y1 != reg2->extents.y1)
310 if (reg1->extents.y2 != reg2->extents.y2)
313 if (PIXREGION_NUMRECTS (reg1) != PIXREGION_NUMRECTS (reg2))
316 rects1 = PIXREGION_RECTS (reg1);
319 for (i = 0; i != PIXREGION_NUMRECTS (reg1); i++)
749 region_type_t * reg1, /* First region in operation */
784 if (PIXREGION_NAR (reg1) || PIXREGION_NAR (reg2)
    [all...]
  /dalvik/vm/compiler/codegen/mips/
CodegenFactory.cpp 48 int reg1)
52 genRegCopy(cUnit, reg1, rlSrc.lowReg);
54 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
58 reg1);
68 int reg1)
70 dvmCompilerClobber(cUnit, reg1);
71 dvmCompilerMarkInUse(cUnit, reg1);
72 loadValueDirect(cUnit, rlSrc, reg1);
284 int reg1, int reg2, int dOffset,
290 res = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2)
    [all...]
  /dalvik/vm/compiler/codegen/
CodegenFactory.cpp 54 int reg1)
58 genRegCopy(cUnit, reg1, rlSrc.lowReg);
60 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
64 reg1);
74 int reg1)
76 dvmCompilerClobber(cUnit, reg1);
77 dvmCompilerMarkInUse(cUnit, reg1);
78 loadValueDirect(cUnit, rlSrc, reg1);
  /dalvik/vm/compiler/codegen/arm/
ArchFactory.cpp 74 int reg1, int reg2, int dOffset,
78 res = opRegReg(cUnit, kOpCmp, reg1, reg2);
  /external/chromium_org/third_party/mesa/src/src/mesa/program/
register_allocate.c 189 struct ra_reg *reg1 = &regs->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1->conflicts[r2] = GL_TRUE
    [all...]
  /external/mesa3d/src/mesa/program/
register_allocate.c 189 struct ra_reg *reg1 = &regs->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1->conflicts[r2] = GL_TRUE
    [all...]
  /art/compiler/dex/quick/x86/
codegen_x86.h 50 bool SameRegType(int reg1, int reg2);
67 void FlushRegWide(int reg1, int reg2);
114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
184 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
185 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
target_x86.cc 104 bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
105 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
316 void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
317 RegisterInfo* info1 = GetRegInfo(reg1);
  /art/compiler/dex/quick/mips/
codegen_mips.h 50 bool SameRegType(int reg1, int reg2);
67 void FlushRegWide(int reg1, int reg2);
114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
int_mips.cc 221 int reg1, int base, int offset, ThrowKind kind) {
226 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
228 NewLIR4(kMipsDiv, r_HI, r_LO, reg1, reg2);
238 RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit,
242 NewLIR4(kMipsDiv, r_HI, r_LO, reg1, t_reg);
253 void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
  /external/v8/src/
regexp-macro-assembler-irregexp.cc 374 void RegExpMacroAssemblerIrregexp::CheckNotRegistersEqual(int reg1,
377 ASSERT(reg1 >= 0);
378 ASSERT(reg1 <= kMaxRegister);
379 Emit(BC_CHECK_NOT_REGS_EQUAL, reg1);
regexp-macro-assembler-tracer.h 62 virtual void CheckNotRegistersEqual(int reg1, int reg2, Label* on_not_equal);
regexp-macro-assembler-tracer.cc 299 void RegExpMacroAssemblerTracer::CheckNotRegistersEqual(int reg1,
302 PrintF(" CheckNotRegistersEqual(reg1=%d, reg2=%d, label[%08x]);\n",
303 reg1,
306 assembler_->CheckNotRegistersEqual(reg1, reg2, on_not_equal);
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sound/
sb.h 335 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
336 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
357 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
360 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
  /art/compiler/dex/quick/arm/
codegen_arm.h 49 bool SameRegType(int reg1, int reg2);
66 void FlushRegWide(int reg1, int reg2);
113 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
159 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);

Completed in 715 milliseconds

1 2 3 4