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    Searched refs:setReg (Results 1 - 25 of 48) sorted by null

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  /external/llvm/lib/CodeGen/
AntiDepBreaker.h 65 MI->getOperand(0).setReg(NewReg);
DeadMachineInstructionElim.cpp 133 nextI = llvm::next(I); // I is invalidated by the setReg
139 UseMI->getOperand(0).setReg(0U);
Spiller.cpp 126 mop.setReg(newLI->reg);
TargetInstrInfo.cpp 164 MI->getOperand(0).setReg(Reg0);
167 MI->getOperand(Idx2).setReg(Reg1);
168 MI->getOperand(Idx1).setReg(Reg2);
228 MO.setReg(Pred[j].getReg());
TailDuplication.cpp 433 MO.setReg(NewReg);
440 MO.setReg(VI->second);
506 II->getOperand(Idx).setReg(SrcReg);
518 II->getOperand(Idx).setReg(Reg);
    [all...]
MachineSSAUpdater.cpp 230 U.setReg(NewVR);
VirtRegMap.cpp 321 MO.setReg(PhysReg);
RegAllocFast.cpp 667 MO.setReg(PhysReg);
672 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
855 MO.setReg(0);
    [all...]
MachineRegisterInfo.cpp 295 O.setReg(ToReg);
PeepholeOptimizer.cpp 292 UseMO->setReg(NewVR);
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 257 MI->getOperand(0).setReg(PeepholeSrc);
295 MI->getOperand(PR).setReg(POrig);
318 Dst.setReg(Src.getReg());
HexagonHardwareLoops.cpp     [all...]
  /external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp 376 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
415 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
449 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
450 RestoreMI->getOperand(1).setReg(SP::G0);
  /external/llvm/lib/Target/R600/
R600EmitClauseMarkers.cpp 147 Consts[i].first->setReg(
151 Consts[i].first->setReg(
R600ControlFlowFinalizer.cpp 191 Srcs[i].first->setReg(LiteralRegs[Index]);
194 Srcs[i].first->setReg(LiteralRegs[Lits.size()]);
R600Packetizer.cpp 136 MI->getOperand(OperandIdx).setReg(It->second);
R600InstrInfo.cpp 910 MO2.setReg(AMDGPU::PRED_SEL_ONE);
913 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
947 PMO.setReg(Pred[2].getReg());
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600InstrInfo.cpp 427 MO2.setReg(AMDGPU::PRED_SEL_ONE);
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
462 PMO.setReg(Pred[2].getReg());
AMDILCFGStructurizer.cpp 346 BlockT *ExitLandBlock, RegiT SetReg);
348 RegiT SetReg);
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600InstrInfo.cpp 427 MO2.setReg(AMDGPU::PRED_SEL_ONE);
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
462 PMO.setReg(Pred[2].getReg());
AMDILCFGStructurizer.cpp 346 BlockT *ExitLandBlock, RegiT SetReg);
348 RegiT SetReg);
    [all...]
  /external/llvm/include/llvm/MC/
MCInst.h 68 /// setReg - Set the register number.
69 void setReg(unsigned Reg) {
  /external/llvm/include/llvm/CodeGen/
MachineOperand.h 337 void setReg(unsigned Reg);
533 /// the setReg method should be used.
ScheduleDAG.h 229 /// setReg - Assign the associated register for this edge. This is
234 void setReg(unsigned Reg) {
236 "setReg called on non-register dependence edge!");
  /external/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 317 MO.setReg(FPReg);
320 MO.setReg(FP8Reg);
323 MO.setReg(BPReg);
326 MO.setReg(BP8Reg);
    [all...]

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