| /external/llvm/test/CodeGen/ARM/ |
| 2012-01-23-PostRA-LICM.ll | 25 %tmp9 = fsub <4 x float> %tmp8, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
50 %tmp33 = fsub <4 x float> %tmp32, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
63 %tmp46 = fsub <4 x float> %tmp45, undef
72 %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
75 %tmp59 = fsub <4 x float> %tmp51, %tmp48
76 %tmp60 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp58
|
| 2009-08-21-PostRAKill.ll | 24 %1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2]
26 %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2]
|
| 2010-04-09-NeonSelect.ll | 8 %1 = fsub <4 x float> %0, undef ; <<4 x float>> [#uses=1]
|
| 2012-04-10-DAGCombine.ll | 15 %tmp10 = fsub float 1.000000e+00, %tmp9
|
| 2011-11-14-EarlyClobber.ll | 38 %sub = fsub double 1.000000e+00, %call
49 %sub16 = fsub double %mul13, %mul15
55 %sub27 = fsub double %mul24, undef
|
| /external/llvm/test/MC/AArch64/ |
| neon-add-sub-instructions.s | 59 fsub v0.2s, v1.2s, v2.2s
60 fsub v0.4s, v1.4s, v2.4s
61 fsub v0.2d, v1.2d, v2.2d
63 // CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e]
64 // CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e]
65 // CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e]
|
| /external/llvm/test/CodeGen/X86/ |
| 2010-05-25-DotDebugLoc.ll | 34 %10 = fsub float %9, %a, !dbg !23 ; <float> [#uses=1]
50 %19 = fsub float %b, %18, !dbg !27 ; <float> [#uses=1]
85 %31 = fsub float %a, %a, !dbg !32 ; <float> [#uses=3]
92 %35 = fsub float %b, %b, !dbg !32 ; <float> [#uses=1]
98 %38 = fsub float %c, %c, !dbg !32 ; <float> [#uses=1]
103 %40 = fsub float %d, %d, !dbg !32 ; <float> [#uses=1]
112 %44 = fsub float %b, %b, !dbg !34 ; <float> [#uses=1]
125 %54 = fsub float %52, %53, !dbg !36 ; <float> [#uses=1]
132 %57 = fsub float %c, %c, !dbg !37 ; <float> [#uses=1]
139 %61 = fsub float %d, %d, !dbg !37 ; <float> [#uses=1
[all...] |
| 2011-03-02-DAGCombiner.ll | 27 %sub = fsub float %tmp, %conv
36 %sub4 = fsub x86_fp80 %conv3, %tmp1
|
| 2007-04-11-InlineAsmVectorResult.ll | 14 %tmp108 = fsub <4 x float> zeroinitializer, %tmp105 ; <<4 x float>> [#uses=0]
|
| 2012-04-09-TwoAddrPassBug.ll | 16 %6 = fsub double %5, undef
|
| 2012-09-13-dagco-fneg.ll | 14 %tmp44.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, float 0.000000e+00>
|
| extract-combine.ll | 10 %sub.i25620 = fsub <4 x float> %conv3.i25615, zeroinitializer ; <<4 x float>> [#uses=1]
|
| /external/clang/test/CodeGen/ |
| fp16-ops.c | 21 // CHECK: fsub float
105 // CHECK: fsub float
110 // CHECK: fsub float
114 // CHECK: fsub float
118 // CHECK: fsub float
242 // CHECK: fsub
247 // CHECK: fsub
251 // CHECK: fsub
|
| ext-vector.c | 81 // CHECK: fsub <4 x float>
90 // CHECK: fsub <4 x float>
99 // CHECK: fsub <4 x float>
108 // CHECK: fsub <4 x float>
|
| /external/llvm/test/CodeGen/NVPTX/ |
| arithmetic-fp-sm20.ll | 21 %ret = fsub double %a, %b
54 %ret = fsub float %a, %b
|
| /external/llvm/test/Transforms/ScalarRepl/ |
| address-space.ll | 11 ; CHECK-NEXT: fsub float
23 %sub = fsub float %tmp5, 5.000000e+00 ; <float> [#uses=1]
|
| /dalvik/dx/tests/102-verify-nonwide-math/ |
| expected.txt | 18 fsub: expected failure occurred
|
| /external/compiler-rt/lib/ |
| subsf3.c | 20 ARM_EABI_FNALIAS(fsub, subsf3)
|
| /external/llvm/test/Bitcode/ |
| function-encoding-rel-operands.ll | 29 %3 = fsub double %2, %2
|
| /external/llvm/test/CodeGen/Mips/ |
| analyzebranch.ll | 17 %sub = fsub double %b, %c.0
|
| /external/llvm/test/CodeGen/PowerPC/ |
| return-val-i128.ll | 17 %tmp5 = fsub float -0.000000e+00, %tmp4 ; <float> [#uses=1]
|
| /external/llvm/test/CodeGen/SPARC/ |
| float.ll | 22 %1 = fsub double -0.000000e+00, %0
|
| /external/llvm/test/Transforms/IndVarSimplify/ |
| 2006-12-10-BitCast.ll | 21 %tmp195.i = fsub float %tmp194.i53, 8.000000e+00 ; <float> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| fpextend.ll | 31 %tmp2 = fsub double -0.000000e+00, %tmp1 ; <double> [#uses=1]
|
| phi-merge-gep.ll | 45 %32 = fsub float %26, %28 ; <float> [#uses=1]
46 %33 = fsub float %27, %29 ; <float> [#uses=1]
56 %43 = fsub float %39, %40 ; <float> [#uses=1]
57 %44 = fsub float %38, %41 ; <float> [#uses=1]
|
