| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| crash_lencod.ll | 50 %sub91 = fsub double %mul89, %mul90
54 %sub96 = fsub double %mul94, %mul95
|
| /external/valgrind/main/none/tests/ppc32/ |
| round.stdout.exp | [all...] |
| /external/valgrind/main/none/tests/ppc64/ |
| round.stdout.exp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 171 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
451 def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>,
453 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
458 def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
465 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
472 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
479 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
486 def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
494 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
[all...] |
| MipsOs16.cpp | 59 case Instruction::FSub:
|
| /external/apache-harmony/luni/src/test/api/common/org/apache/harmony/luni/tests/java/io/ |
| SerializationStressTest3.java | 120 int fsub; field in class:SerializationStressTest3.DefaultConstructorSub
126 fsub = subValueAfterConstructor;
144 return inst.fsub == subValueAfterConstructor;
178 int fsub; field in class:SerializationStressTest3.PrivateConstructorSub
185 fsub = subValueAfterConstructor;
202 && inst.fsub == subValueAfterConstructor;
236 int fsub; field in class:SerializationStressTest3.ProtectedConstructorSub
242 fsub = subValueAfterConstructor;
259 && inst.fsub == subValueAfterConstructor;
293 int fsub; field in class:SerializationStressTest3.PublicConstructorSub
[all...] |
| /external/llvm/test/CodeGen/R600/ |
| schedule-vs-if-nested-loop.ll | 12 %6 = fsub float -0.000000e+00, %5
104 %81 = fsub float -0.000000e+00, %80
114 %88 = fsub float -0.000000e+00, %87
|
| jump-address.ll | 45 %22 = fsub float -0.000000e+00, %21
|
| schedule-if.ll | 41 %22 = fsub float -0.000000e+00, %21
|
| /external/clang/test/CodeGen/ |
| exprs.c | 145 // CHECK: fsub double -0.0
|
| /external/javassist/src/main/javassist/bytecode/ |
| Mnemonic.java | 140 "fsub", /* 102*/
|
| /external/llvm/bindings/python/llvm/ |
| enumerations.py | 72 ('FSub', 11),
|
| /external/llvm/test/CodeGen/ARM/ |
| fnegs.ll | 11 %1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
|
| 2009-10-02-NEONSubregsBug.ll | 15 %6 = fsub <4 x float> zeroinitializer, %3 ; <<4 x float>> [#uses=1]
37 %28 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %5 ; <<4 x float>> [#uses=1]
|
| spill-q.ll | 63 %14 = fsub <4 x float> %12, %13 ; <<4 x float>> [#uses=1]
64 %15 = fsub <4 x float> %14, undef ; <<4 x float>> [#uses=1]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-cmp-04.ll | 92 %res = fsub float %a, %cur
131 %res = fsub float -0.0, %abs
150 %res = fsub float -0.0, %a
217 %sub = fsub float %c, %add
|
| /external/llvm/test/CodeGen/X86/ |
| avx-arith.ll | 34 %sub.i = fsub <4 x double> %x, %y
42 %sub.i = fsub <4 x double> %y, %tmp2
49 %sub.i = fsub <8 x float> %x, %y
57 %sub.i = fsub <8 x float> %y, %tmp2
|
| vec_logical.ll | 7 %tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding-fp.s | 81 # CHECK: fsub 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x28]
82 fsub 2, 3, 4
83 # CHECK: fsub. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x29]
84 fsub. 2, 3, 4
|
| /external/llvm/test/Transforms/ScalarRepl/ |
| inline-vector.ll | 37 %sub.i.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp10.i
|
| /external/valgrind/main/auxprogs/ |
| ppcfround.c | 254 INSN(fsub, "fsub %%f4, %%f1,%%f2");
255 INSN(fsub_, "fsub. %%f4, %%f1,%%f2");
469 do_N_binary("fsub", insn_fsub, args, nargs, SHOW_ALL);
|
| /external/valgrind/main/none/tests/amd64/ |
| insn_fpu.def | 347 fsub st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[-7530.8643]
348 fsub st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-9999.9999]
349 fsub st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[9999.9999]
350 fsub st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[7530.8643]
351 fsub st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-6419753.3580246]
352 fsub st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-8888888.8888888]
353 fsub st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[8888888.8888888]
354 fsub st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[6419753.3580246]
355 fsub st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[7530.8643]
356 fsub st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[9999.9999
[all...] |
| /external/valgrind/main/none/tests/x86/ |
| insn_fpu.def | 347 fsub st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[-7530.8643]
348 fsub st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-9999.9999]
349 fsub st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[9999.9999]
350 fsub st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[7530.8643]
351 fsub st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-6419753.3580246]
352 fsub st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-8888888.8888888]
353 fsub st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[8888888.8888888]
354 fsub st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[6419753.3580246]
355 fsub st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[7530.8643]
356 fsub st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[9999.9999
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-spill-q.ll | 63 %14 = fsub <4 x float> %12, %13 ; <<4 x float>> [#uses=1]
64 %15 = fsub <4 x float> %14, undef ; <<4 x float>> [#uses=1]
|
| /external/llvm/test/MC/X86/ |
| intel-syntax.s | 543 // CHECK: fsub %st(1)
549 fsub ST(0), ST(1) label
557 // CHECK: fsub %st(0), %st(1)
562 fsub ST(1), ST(0) label
569 // CHECK: fsub %st(1)
575 fsub ST(1) label
|
