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  /external/chromium_org/third_party/openssl/openssl/crypto/modes/asm/
ghash-x86.pl 422 &movz ($Zll,&BP(15,$inp));
597 &movz ($Zll,&BP(15,$inp));
733 &movz ($rem[1],&LB($rem[1])) if ($i>0);
759 &movz ($rem[1],&LB($rem[1]));
773 &movz ($rem[0],&LB($rem[0]));
    [all...]
  /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/
x86_64-xlate.pl 116 if ($self->{op} =~ /^(movz)x?([bw]).*/) { # movz is pain...
143 if ($self->{op} eq "movz") { # movz is pain...
160 $self->{op} =~ s/^movz/movzx/;
    [all...]
  /external/openssl/crypto/modes/asm/
ghash-x86.pl 422 &movz ($Zll,&BP(15,$inp));
597 &movz ($Zll,&BP(15,$inp));
733 &movz ($rem[1],&LB($rem[1])) if ($i>0);
759 &movz ($rem[1],&LB($rem[1]));
773 &movz ($rem[0],&LB($rem[0]));
    [all...]
  /external/openssl/crypto/perlasm/
x86_64-xlate.pl 116 if ($self->{op} =~ /^(movz)x?([bw]).*/) { # movz is pain...
143 if ($self->{op} eq "movz") { # movz is pain...
160 $self->{op} =~ s/^movz/movzx/;
    [all...]
  /dalvik/vm/compiler/codegen/mips/
GlobalOptimizations.cpp 146 insnCount = 0; /* movz relies on thisLIR setting dst reg so abandon propagation*/
MipsLIR.h 436 kMipsMovz, /* movz d,s,t [000000] s[25..21] t[20..16] d[15..11] [00000001010] */
  /external/llvm/lib/ExecutionEngine/RuntimeDyld/
RuntimeDyldImpl.h 170 return 20; // movz; movk; movk; movk; br
RuntimeDyld.cpp 365 *StubAddr = 0xd2e00010; // movz ip0, #:abs_g3:<addr>
  /external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/
aes-x86_64.pl 1263 movz %dl,%esi # rk[i]>>0
1265 movz %dh,%esi # rk[i]>>8
1271 movz %dl,%esi # rk[i]>>16
1275 movz %dh,%esi # rk[i]>>24
1461 movz %dl,%esi # rk[11]>>0
1463 movz %dh,%esi # rk[11]>>8
1469 movz %dl,%esi # rk[11]>>16
1473 movz %dh,%esi # rk[11]>>24
    [all...]
aesni-x86.pl     [all...]
  /external/chromium_org/v8/src/mips/
disasm-mips.cc 754 case MOVZ:
755 Format(instr, "movz 'rd, 'rs, 'rt");
constants-mips.h 318 MOVZ = ((1 << 3) + 2),
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 613 // we'll use a movz/movk or movn/movk sequence.
655 // literal-pool load, or even a hypothetical movz/movk/add sequence
  /external/openssl/crypto/aes/asm/
aes-x86_64.pl 1263 movz %dl,%esi # rk[i]>>0
1265 movz %dh,%esi # rk[i]>>8
1271 movz %dl,%esi # rk[i]>>16
1275 movz %dh,%esi # rk[i]>>24
1461 movz %dl,%esi # rk[11]>>0
1463 movz %dh,%esi # rk[11]>>8
1469 movz %dl,%esi # rk[11]>>16
1473 movz %dh,%esi # rk[11]>>24
    [all...]
aesni-x86.pl     [all...]
  /external/v8/src/mips/
disasm-mips.cc 741 case MOVZ:
742 Format(instr, "movz 'rd, 'rs, 'rt");
stub-cache-mips.cc     [all...]
constants-mips.h 313 MOVZ = ((1 << 3) + 2),
  /external/llvm/test/MC/AArch64/
basic-a64-instructions.s     [all...]
  /external/valgrind/main/VEX/priv/
guest_mips_toIR.c     [all...]
  /external/chromium_org/v8/test/cctest/
test-assembler-mips.cc 223 __ Movz(a0, t6, t7); // a0 not updated (t7 is NOT 0).
226 __ Movz(a0, t6, v1); // a0<-t6, v0 is 0, from 8 instr back.
    [all...]
  /external/v8/test/cctest/
test-assembler-mips.cc 233 __ Movz(a0, t6, t7); // a0 not updated (t7 is NOT 0).
236 __ Movz(a0, t6, v1); // a0<-t6, v0 is 0, from 8 instr back.
    [all...]
  /art/compiler/dex/quick/mips/
mips_lir.h 343 kMipsMovz, // movz d,s,t [000000] s[25..21] t[20..16] d[15..11] [00000001010].
  /external/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.cpp 1071 // If high bits are set then a 32-bit MOVZ can't possibly work.
    [all...]
  /system/core/libpixelflinger/codeflinger/
MIPSAssembler.h 351 void MOVZ(int Rd, int Rs, int Rt);

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