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  /external/chromium_org/base/
atomicops_internals_x86_gcc.cc 43 false, // no SSE2
84 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
  /external/chromium_org/third_party/angle_dx11/src/libGLESv2/renderer/
ImageSSE2.cpp 8 // ImageSSE2.cpp: Implements SSE2-based functions of rx::Image class. It's
10 // not for code blocks that use SSE2 explicitly.
  /external/llvm/test/CodeGen/X86/
fast-isel-store.ll 1 ; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
2 ; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
vec_shuffle-14.ll 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X86-32
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s -check-prefix=X86-64
vshift-1.ll 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
3 ; test vector shifts converted to proper SSE2 vector shifts when the shift
vshift-2.ll 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
3 ; test vector shifts converted to proper SSE2 vector shifts when the shift
vshift-3.ll 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
3 ; test vector shifts converted to proper SSE2 vector shifts when the shift
2006-08-07-CycleInDAG.ll 1 ; RUN: llc < %s -march=x86 -mattr=+sse2
2007-11-06-InstrSched.ll 1 ; RUN: llc < %s -march=x86 -mcpu=generic -mattr=+sse2 | not grep lea
avx-vinsertf128.ll 20 declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
22 declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
30 %vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
31 %ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
crash-nosse.ll 1 ; RUN: llc < %s -mcpu=corei7 -mattr=-sse2,-sse41 -verify-machineinstrs
mmx-arg-passing.ll 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64
  /external/llvm/test/Transforms/InstCombine/
vec_demanded_elts.ll 66 %tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
69 %tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
72 %tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
75 %tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
135 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
136 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
137 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
138 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
  /external/oprofile/events/i386/core/
unit_masks 43 0x02 SSE2 Packed-Double
44 0x03 SSE2 Scalar-Double
  /frameworks/rs/driver/runtime/
Android.mk 52 # so far, there is no such device with SSE2 only.
86 # Build an optimized version of the library if the device is SSE2- or above
  /external/chromium_org/third_party/mesa/src/src/mesa/main/
cpuinfo.c 78 strcat(buffer, (cpu_has_xmm2) ? "/SSE2" : "/SSE");
  /external/chromium_org/third_party/qcms/
README.chromium 29 - Only reference code from transform-sse1.c and transform-sse2.c when SSE is
  /external/compiler-rt/lib/i386/
ashldi3.S 35 #else // Use GPRs instead of SSE2 instructions, if they aren't available.
lshrdi3.S 35 #else // Use GPRs instead of SSE2 instructions, if they aren't available.
  /external/eigen/bench/btl/
CMakeLists.txt 28 SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} /arch:SSE2")
  /external/elfutils/backends/
i386_auxv.c 44 "fxsr\0" "sse\0" "sse2\0" "ss\0" "ht\0" "tm\0" "ia64\0" "pbe\0" "\0";
  /external/libvpx/libvpx/test/
test_libvpx.cc 41 append_gtest_filter(":-SSE2/*");
  /external/libvpx/libvpx/vp9/encoder/x86/
vp9_error_sse2.asm 18 INIT_XMM sse2
vp9_sad_sse2.asm 84 INIT_XMM sse2
127 INIT_XMM sse2
173 INIT_XMM sse2
217 INIT_XMM sse2
  /external/libyuv/files/include/libyuv/
cpu_id.h 46 // Detect CPU has SSE2 etc.

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