| /external/llvm/test/CodeGen/X86/ |
| phys_subreg_coalesce.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | FileCheck %s
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| pr2656.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
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| vec_extract.ll | 1 ; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse41 -o %t
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| vec_set-4.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pinsrw | count 2
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| 2006-05-11-InstrSched.ll | 2 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats 2>&1 | \
34 %tmp99 = tail call <4 x i32> @llvm.x86.sse2.psra.d( <4 x i32> %tmp88, <4 x i32> %tmp55 ) ; <<4 x i32>> [#uses=1]
52 declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>)
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| vec_ss_load_fold.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse,+sse2,+sse41 | FileCheck %s
77 %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double
86 declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
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| 2006-05-01-SchedCausingSpills.ll | 21 %tmp98 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp75, <4 x i32> %tmp89 ) ; <<4 x i32>> [#uses=1]
36 %tmp159 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp134, <4 x i32> %tmp148 ) ; <<4 x i32>> [#uses=1]
51 %tmp220 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp195, <4 x i32> %tmp209 ) ; <<4 x i32>> [#uses=1]
66 %tmp281 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp256, <4 x i32> %tmp270 ) ; <<4 x i32>> [#uses=1]
77 declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)
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| /external/mesa3d/src/mesa/main/ |
| cpuinfo.c | 78 strcat(buffer, (cpu_has_xmm2) ? "/SSE2" : "/SSE");
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| /external/qemu/distrib/sdl-1.2.15/include/ |
| SDL_cpuinfo.h | 57 /** This function returns true if the CPU has SSE2 features */
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| /external/stressapptest/src/ |
| adler32memcpy.h | 54 // x86_64 SSE2 assembly implementation of fast and stressful Adler memory copy.
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| /prebuilts/tools/darwin-x86/sdl/include/SDL/ |
| SDL_cpuinfo.h | 57 /** This function returns true if the CPU has SSE2 features */
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| /prebuilts/tools/linux-x86/sdl/include/SDL/ |
| SDL_cpuinfo.h | 57 /** This function returns true if the CPU has SSE2 features */
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| /prebuilts/tools/windows/sdl/include/SDL/ |
| SDL_cpuinfo.h | 57 /** This function returns true if the CPU has SSE2 features */
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| /external/chromium_org/third_party/skia/src/opts/ |
| opts_check_SSE2.cpp | 25 gcc may generate sse2 even for scalar ops (and thus give an invalid
71 /* All x86_64 machines have SSE2, or we know it's supported at compile time, so don't even bother checking. */
204 // The SSE2 version is not (yet) faster for black, so we check
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| /external/oprofile/events/i386/p4/ |
| events | 36 event:0x13 counters:2,6 um:flame_uop minimum:3000 name:SSE_INPUT_ASSIST : input assists requested for SSE or SSE2 operands
42 event:0x19 counters:2,6 um:flame_uop minimum:3000 name:128BIT_MMX_UOP : 128 bit integer SIMD SSE2 uops
44 event:0x1b counters:2,6 um:x87_simd_moves_uop minimum:3000 name:X87_SIMD_MOVES_UOP : x87 FPU, MMX, SSE, or SSE2 loads, stores and reg-to-reg moves
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| /external/skia/src/opts/ |
| opts_check_SSE2.cpp | 25 gcc may generate sse2 even for scalar ops (and thus give an invalid
71 /* All x86_64 machines have SSE2, or we know it's supported at compile time, so don't even bother checking. */
204 // The SSE2 version is not (yet) faster for black, so we check
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| /frameworks/rs/driver/runtime/arch/ |
| x86_sse3.ll | 4 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
20 %4 = tail call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %3, i32 32)
54 %4 = tail call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %3, i32 32)
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| /external/eigen/Eigen/ |
| Core | 173 return "SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2";
175 return "SSE, SSE2, SSE3, SSSE3, SSE4.1";
177 return "SSE, SSE2, SSE3, SSSE3";
179 return "SSE, SSE2, SSE3";
181 return "SSE, SSE2";
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| /external/oprofile/events/i386/core_2/ |
| unit_masks | 164 0x04 Retired SSE2 packed-double instructions
165 0x08 Retired SSE2 scalar-double instructions
166 0x10 Retired SSE2 vector integer instructions
171 0x04 Retired computational SSE2 packed-double instructions
172 0x08 Retired computational SSE2 scalar-double instructions
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| /external/chromium_org/v8/src/ia32/ |
| lithium-gap-resolver-ia32.cc | 321 if (CpuFeatures::IsSupported(SSE2)) {
322 CpuFeatureScope scope(cgen_->masm(), SSE2);
354 if (CpuFeatures::IsSupported(SSE2)) {
355 CpuFeatureScope scope(cgen_->masm(), SSE2);
367 // be a double stack slot in the non-SSE2 case.
374 if (CpuFeatures::IsSupported(SSE2)) {
375 CpuFeatureScope scope(cgen_->masm(), SSE2);
471 CpuFeatureScope scope(cgen_->masm(), SSE2);
480 CpuFeatureScope scope(cgen_->masm(), SSE2);
493 CpuFeatureScope scope(cgen_->masm(), SSE2);
[all...] |
| lithium-codegen-ia32.cc | 45 return CpuFeatures::IsSafeForSnapshot(SSE2) ? kSaveFPRegs : kDontSaveFPRegs;
270 if (info()->saves_caller_doubles() && CpuFeatures::IsSupported(SSE2)) {
272 CpuFeatureScope scope(masm(), SSE2);
356 if (!CpuFeatures::IsSupported(SSE2)) FlushX87StackIfNecessary(instr);
362 if (!CpuFeatures::IsSupported(SSE2)) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_logic.c | 194 pcmpeq = "llvm.x86.sse2.pcmpeq.b";
195 pcmpgt = "llvm.x86.sse2.pcmpgt.b";
198 pcmpeq = "llvm.x86.sse2.pcmpeq.w";
199 pcmpgt = "llvm.x86.sse2.pcmpgt.w";
202 pcmpeq = "llvm.x86.sse2.pcmpeq.d";
203 pcmpgt = "llvm.x86.sse2.pcmpgt.d";
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_logic.c | 194 pcmpeq = "llvm.x86.sse2.pcmpeq.b";
195 pcmpgt = "llvm.x86.sse2.pcmpgt.b";
198 pcmpeq = "llvm.x86.sse2.pcmpeq.w";
199 pcmpgt = "llvm.x86.sse2.pcmpgt.w";
202 pcmpeq = "llvm.x86.sse2.pcmpeq.d";
203 pcmpgt = "llvm.x86.sse2.pcmpgt.d";
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| /external/libvpx/libvpx/build/make/ |
| rtcd.sh | 330 ALL_ARCHS=$(filter mmx sse sse2 sse3 ssse3 sse4_1 avx avx2)
334 ALL_ARCHS=$(filter mmx sse sse2 sse3 ssse3 sse4_1 avx avx2)
335 REQUIRES=${REQUIRES:-mmx sse sse2}
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| /external/chromium_org/third_party/libjingle/source/talk/media/base/ |
| cpuid.h | 61 // Detect CPU has SSE2 etc.
|
