| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_conv.c | 427 /* relying on clamping behavior of sse2 intrinsics here */
488 /* relying on clamping behavior of sse2 intrinsics here */
|
| /external/mesa3d/src/mesa/x86/ |
| read_rgba_span_x86.S | 251 * functionality wasn't introduced until SSE2 with the MOVDQ2Q
337 * SSE2 optimized version of the BGRA8888_REV to RGBA copy routine.
|
| /external/openssl/crypto/rc4/asm/ |
| rc4-586.pl | 53 # is guarded by SSE2 bit (see below), not MMX/SSE.
192 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
|
| /external/oprofile/events/i386/core_2/ |
| events | 120 event:0xc7 counters:0,1 um:simd_inst_retired minimum:500 name:SIMD_INST_RETIRED : SSE/SSE2 instructions retired
123 event:0xca counters:0,1 um:simd_comp_inst_retired minimum:500 name:SIMD_COMP_INST_RETIRED : Retired computational SSE/SSE2 instructions
|
| /external/oprofile/events/i386/westmere/ |
| unit_masks | 84 0x04 sse_fp SSE and SSE2 FP Uops
85 0x08 sse2_integer SSE2 integer Uops
|
| /external/skia/src/opts/ |
| SkBitmapProcState_opts_SSE2.cpp | 307 // SSE2 only support 16bit interger max & min, so only process the case
436 // SSE2 only support 16bit interger max & min, so only process the case
|
| /external/v8/src/ia32/ |
| code-stubs-ia32.h | 633 CpuFeatures::Scope scope(SSE2);
647 CpuFeatures::Scope scope(SSE2);
|
| macro-assembler-ia32.cc | 442 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
443 CpuFeatures::Scope use_sse2(SSE2);
462 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
463 CpuFeatures::Scope use_sse2(SSE2);
475 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
476 CpuFeatures::Scope fscope(SSE2);
677 CpuFeatures::Scope scope(SSE2);
723 CpuFeatures::Scope scope(SSE2);
[all...] |
| /external/valgrind/main/exp-bbv/tests/amd64-linux/ |
| ll.S | 587 .ascii "flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc pebs bts pni dtes64 monitor ds_cpl vmx est cid cx16 xtpr pdcm lahf_lm tpr_shadow\n"
612 .ascii "flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc pebs bts pni dtes64 monitor ds_cpl vmx est cid cx16 xtpr pdcm lahf_lm tpr_shadow\n"
|
| /external/webrtc/src/modules/audio_processing/aec/ |
| aec_rdft.c | 29 // constants shared by all paths (C, SSE2).
34 // constants used by SSE2 but initialized in C path.
|
| /external/valgrind/main/VEX/pub/ |
| libvex.h | 68 together, although some combinations don't make sense. (eg, SSE2
75 #define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */
79 /* amd64: baseline capability is SSE2, with cmpxchg8b but not
|
| /bionic/libc/arch-x86/string/ |
| ssse3-strcat-atom.S | 110 #include "sse2-strlen-atom.S"
|
| /external/chromium_org/chrome/common/ |
| chrome_content_client.cc | 366 // For Linux ia32, Flapper requires SSE2.
|
| /external/chromium_org/media/base/simd/ |
| convert_rgb_to_yuv_ssse3.asm | 9 ; This file uses SSE, SSE2, SSE3, and SSSE3, which are supported by all ATOM
|
| /external/chromium_org/media/base/ |
| video_frame.cc | 260 // This is sufficient for MMX and SSE2 reads (movq/movdqa).
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_format_aos.c | 234 /* UIToFP can't be expressed in SSE2 */
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/rtasm/ |
| rtasm_x86sse.h | 34 * for mmx/sse/sse2 support on the cpu.
|
| /external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
| x86_64-gf2m.pl | 117 movq (%rsp,$i0,8),$R # half of calculations is done in SSE2
|
| /external/chromium_org/third_party/skia/src/utils/ |
| SkSHA1.cpp | 94 //return _mm_or_ps(_mm_andnot_ps(B, D), _mm_and_ps(B, C)); //SSE2
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/base/ |
| atomicops-internals-x86.h | 56 bool has_sse2; // Processor has SSE2.
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/base/ |
| atomicops-internals-x86.h | 56 bool has_sse2; // Processor has SSE2.
|
| /external/chromium_org/v8/src/ia32/ |
| lithium-codegen-ia32.h | 118 // Support for non-sse2 (x87) floating point stack handling.
|
| /external/clang/include/clang/Basic/ |
| BuiltinsX86.def | 137 // MMX+SSE2
[all...] |
| /external/eigen/Eigen/src/LU/arch/ |
| Inverse_SSE.h | 14 // http://software.intel.com/en-us/articles/optimized-matrix-library-for-use-with-the-intel-pentiumr-4-processors-sse2-instructions/
|
| /external/llvm/test/CodeGen/X86/ |
| mult-alt-x86.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2
|
