| /external/v8/src/mips/ |
| constants-mips.cc | 332 case SWL:
|
| disasm-mips.cc | 898 case SWL:
899 Format(instr, "swl 'rt, 'imm16s('rs)");
|
| constants-mips.h | 290 SWL = ((5 << 3) + 2) << kOpcodeShift,
|
| assembler-mips.cc | 1439 void Assembler::swl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| assembler-mips.h | 754 void swl(Register rd, const MemOperand& rs);
[all...] |
| /system/core/libcutils/tests/memset_mips/ |
| memset_cmips.S | 50 # define SWHI swl /* high part is left in big-endian */
|
| /external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/ |
| aes-mips.pl | 410 swl $s0,0+$MSB($out)
411 swl $s1,4+$MSB($out)
412 swl $s2,8+$MSB($out)
413 swl $s3,12+$MSB($out)
747 swl $s0,0+$MSB($out)
748 swl $s1,4+$MSB($out)
749 swl $s2,8+$MSB($out)
750 swl $s3,12+$MSB($out)
[all...] |
| aes-mips.S | 292 swl $8,0+3($5)
293 swl $9,4+3($5)
294 swl $10,8+3($5)
295 swl $11,12+3($5)
599 swl $8,0+3($5)
600 swl $9,4+3($5)
601 swl $10,8+3($5)
602 swl $11,12+3($5)
|
| /external/openssl/crypto/aes/asm/ |
| aes-mips.pl | 410 swl $s0,0+$MSB($out)
411 swl $s1,4+$MSB($out)
412 swl $s2,8+$MSB($out)
413 swl $s3,12+$MSB($out)
747 swl $s0,0+$MSB($out)
748 swl $s1,4+$MSB($out)
749 swl $s2,8+$MSB($out)
750 swl $s3,12+$MSB($out)
[all...] |
| aes-mips.S | 292 swl $8,0+3($5)
293 swl $9,4+3($5)
294 swl $10,8+3($5)
295 swl $11,12+3($5)
599 swl $8,0+3($5)
600 swl $9,4+3($5)
601 swl $10,8+3($5)
602 swl $11,12+3($5)
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 158 SWL,
|
| MipsInstrInfo.td | 134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
[all...] |
| Mips64InstrInfo.td | 155 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>;
|
| MipsISelLowering.cpp | 185 case MipsISD::SWL: return "MipsISD::SWL";
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 410 # CHECK: swl $4, 16($5)
|
| mips32_le.txt | 416 # CHECK: swl $4, 16($5)
|
| mips32r2.txt | 413 # CHECK: swl $4, 16($5)
|
| mips32r2_le.txt | 413 # CHECK: swl $4, 16($5)
|
| /external/chromium_org/v8/src/mips/ |
| disasm-mips.cc | 911 case SWL:
912 Format(instr, "swl 'rt, 'imm16s('rs)");
|
| constants-mips.h | 293 SWL = ((5 << 3) + 2) << kOpcodeShift,
|
| assembler-mips.cc | 1446 void Assembler::swl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| assembler-mips.h | 689 void swl(Register rd, const MemOperand& rs);
[all...] |
| /external/chromium/net/base/ |
| mime_util.cc | 120 { "application/x-shockwave-flash", "swf,swl" }
|
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 74 /*40 */ "sb ", "sh ", "swl", "sw ", "sdl", "sdr", "swr", "cache",
|
| /external/chromium_org/net/base/ |
| mime_util.cc | 163 { "application/x-shockwave-flash", "swf,swl" },
[all...] |
