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  /external/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 189 { ISD::FP_EXTEND, MVT::v4f32, 4 }
235 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
244 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
246 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
247 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
248 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
249 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
259 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }
    [all...]
ARMCallingConv.td 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
89 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
139 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
149 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
167 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
179 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
ARMInstrNEON.td     [all...]
  /external/llvm/test/CodeGen/R600/
store.r600.ll 15 ; v4f32 store
  /frameworks/rs/driver/runtime/
math.ll 9 declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
  /external/llvm/test/CodeGen/ARM/
coalesce-subregs.ll 17 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
21 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
30 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
34 %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
36 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
45 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
55 %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
58 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
67 declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
68 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwin
    [all...]
vld1.ll 108 %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
129 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
136 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1)
vst2.ll 109 call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
126 call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
140 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
  /external/llvm/lib/Target/X86/
X86InstrAVX512.td 22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>
    [all...]
X86InstrFMA.td 78 memopv8f32, X86Fmadd, v4f32, v8f32>;
80 memopv8f32, X86Fmsub, v4f32, v8f32>;
83 v4f32, v8f32>;
86 v4f32, v8f32>;
105 memopv8f32, X86Fnmadd, v4f32, v8f32>;
107 memopv8f32, X86Fnmsub, v4f32, v8f32>;
340 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
342 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
344 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
346 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32
    [all...]
X86InstrSSE.td 250 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
251 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
259 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
260 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
281 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
290 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
307 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
312 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>
    [all...]
X86CallingConv.td 43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
100 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
216 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
244 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
267 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
293 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
315 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
365 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
374 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
487 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64]
    [all...]
X86InstrFragmentsSIMD.td 84 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
85 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
229 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
236 def ssmem : Operand<v4f32> {
255 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
304 (v4f32 (alignedload node:$ptr))>;
335 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
381 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
  /external/llvm/test/CodeGen/Thumb2/
crash.ll 56 %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %p, i32 1)
58 tail call void @llvm.arm.neon.vst1.v4f32(i8* %p, <4 x float> %vld1, i32 1)
62 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
64 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
  /external/llvm/lib/Target/AArch64/
AArch64InstrNEON.td 163 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
185 v2f32, v4f32, v2f64, 1>;
191 v2f32, v4f32, v2f64, 0>;
197 v2f32, v4f32, v2f64, 1>;
264 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
271 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
281 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
288 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
296 v2f32, v4f32, v2f64, 0>
    [all...]
  /external/llvm/test/CodeGen/AArch64/
neon-fma.ll 50 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
61 %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
81 %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %negA, <4 x float> %B, <4 x float> %C)
93 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>)
104 %val = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
neon-add-pairwise.ll 69 declare <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float>, <4 x float>)
81 %val = call <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float> %lhs, <4 x float> %rhs)
neon-max-min-pairwise.ll 212 declare <4 x float> @llvm.arm.neon.vpmaxs.v4f32(<4 x float>, <4 x float>)
224 %val = call <4 x float> @llvm.arm.neon.vpmaxs.v4f32(<4 x float> %lhs, <4 x float> %rhs)
237 declare <4 x float> @llvm.arm.neon.vpmins.v4f32(<4 x float>, <4 x float>)
249 %val = call <4 x float> @llvm.arm.neon.vpmins.v4f32(<4 x float> %lhs, <4 x float> %rhs)
262 declare <4 x float> @llvm.aarch64.neon.vpmaxnm.v4f32(<4 x float>, <4 x float>)
274 %val = call <4 x float> @llvm.aarch64.neon.vpmaxnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
287 declare <4 x float> @llvm.aarch64.neon.vpminnm.v4f32(<4 x float>, <4 x float>)
299 %val = call <4 x float> @llvm.aarch64.neon.vpminnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
neon-max-min.ll 212 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>)
224 %val = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %lhs, <4 x float> %rhs)
237 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>)
249 %val = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %lhs, <4 x float> %rhs)
263 declare <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float>, <4 x float>)
275 %val = call <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
288 declare <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float>, <4 x float>)
300 %val = call <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
  /external/llvm/lib/Target/PowerPC/
PPCCallingConv.td 36 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
69 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
83 CCIfType<[v16i8, v8i16, v4i32, v4f32],
  /external/llvm/test/CodeGen/PowerPC/
recipest.ll 8 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
105 %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
215 %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
vec_fmuladd.ll 7 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>)
23 %fmuladd = call <4 x float> @llvm.fmuladd.v4f32 (<4 x float> %x, <4 x float> %x, <4 x float> %x)
vec_sqrt.ll 10 declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %val)
29 %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
  /external/llvm/lib/Target/R600/
AMDGPUCallingConv.td 41 CCIfType<[v4i32, v4f32], CCAssignToStack <16, 16>>,
R600Instructions.td 379 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
474 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
480 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
486 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
491 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
494 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
505 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
510 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
515 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
520 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src)
    [all...]

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