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  /frameworks/rs/driver/runtime/arch/
neon.ll 9 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
18 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
39 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
42 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
107 %1 = tail call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %value, <4 x float> %high) nounwind readnone
108 %2 = tail call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %1, <4 x float> %low) nounwind readnone
123 %a = tail call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %_value, <4 x float> %_high) nounwind readnone
124 %b = tail call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %a, <4 x float> %_low) nounwind readnone
133 %a = tail call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %_value, <4 x float> %_high) nounwind readnone
134 %b = tail call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %a, <4 x float> %_low) nounwind readnon
    [all...]
x86_sse2.ll 12 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readnone
100 %1 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) nounwind readnone
  /external/llvm/test/Transforms/LoopVectorize/
intrinsic.ll 7 ;CHECK: llvm.sqrt.v4f32
59 ;CHECK: llvm.sin.v4f32
111 ;CHECK: llvm.cos.v4f32
163 ;CHECK: llvm.exp.v4f32
215 ;CHECK: llvm.exp2.v4f32
267 ;CHECK: llvm.log.v4f32
319 ;CHECK: llvm.log10.v4f32
371 ;CHECK: llvm.log2.v4f32
423 ;CHECK: llvm.fabs.v4f32
472 ;CHECK: llvm.floor.v4f32
    [all...]
  /external/llvm/test/CodeGen/ARM/
vst4.ll 100 call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
112 call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
127 declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
2009-10-02-NEONSubregsBug.ll 38 %29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
63 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
vabs.ll 63 %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
75 declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
vst1.ll 107 call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1)
129 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
vst3.ll 115 call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
128 declare void @llvm.arm.neon.vst3.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
vstlane.ll 183 call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
194 declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
269 call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
280 declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
357 call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
375 declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
vld2.ll 139 %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1)
155 declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
vld3.ll 143 %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8* %tmp0, i32 1)
159 declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8*, i32) nounwind readonly
vld4.ll 144 %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0, i32 1)
160 declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*, i32) nounwind readonly
  /external/clang/test/CodeGen/
x86_64-arguments.c 155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
156 v4f32 f25(v4f32 X) {
179 v4f32 v;
  /external/llvm/lib/Target/R600/
AMDGPUISelLowering.cpp 64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
76 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
86 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
94 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
SIInstructions.td     [all...]
SIGenRegisterInfo.pl 184 my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32'));
188 my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32'));
R600Instructions.td 1065 def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
    [all...]
R600GenRegisterInfo.pl 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
  /external/mesa3d/src/gallium/drivers/radeon/
SIInstructions.td     [all...]
SIGenRegisterInfo.pl 184 my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32'));
188 my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32'));
R600Instructions.td 1065 def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
    [all...]
  /external/llvm/lib/IR/
AutoUpgrade.cpp 29 // changed their type from v4f32 to v2i64.
33 // v4f32 arguments.
344 // The arguments for these intrinsics used to be v4f32, and changed
ValueTypes.cpp 161 case MVT::v4f32: return "v4f32";
224 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
  /external/llvm/lib/Target/NVPTX/
NVPTXVector.td 97 // Extract v4f32
102 (v4f32 V4F32Regs:$src), imm:$c))],
188 // Insert v4f32
289 def V4F32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "f32")>, OpNode,
    [all...]
  /external/llvm/include/llvm/CodeGen/
ValueTypes.h 98 v4f32 = 43, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
292 case v4f32:
328 case v4f32:
393 case v4f32:
527 if (NumElements == 4) return MVT::v4f32;

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