/external/llvm/lib/Target/XCore/ |
XCoreTargetMachine.h | 36 StringRef CPU, StringRef FS, const TargetOptions &Options,
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUTargetMachine.h | 42 StringRef CPU,
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/external/qemu/ |
dyngen-exec.h | 64 #error unsupported CPU
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/external/v8/src/ia32/ |
assembler-ia32-inl.h | 42 #include "cpu.h" 54 CPU::FlushICache(p, sizeof(uint32_t)); 60 CPU::FlushICache(p, sizeof(uint32_t)); 66 CPU::FlushICache(p, sizeof(uint32_t)); 71 CPU::FlushICache(p, sizeof(uint32_t)); 127 CPU::FlushICache(pc_, sizeof(Address)); 165 CPU::FlushICache(pc_, sizeof(Address)); 225 CPU::FlushICache(pc_, sizeof(Address)); 232 CPU::FlushICache(pc_, sizeof(Address)); 253 CPU::FlushICache(pc_, sizeof(Address)) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
AMDGPUMCTargetDesc.cpp | 49 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 52 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
NVPTXMCTargetDesc.cpp | 48 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { 50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
AMDGPUMCTargetDesc.cpp | 50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 53 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
SparcMCTargetDesc.cpp | 46 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, 49 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/XCore/MCTargetDesc/ |
XCoreMCTargetDesc.cpp | 47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, 50 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
AMDGPUMCTargetDesc.cpp | 49 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 52 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCTargetDesc.cpp | 40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { 58 bool NoCPU = CPU == "generic" || CPU.empty(); 72 // Use CPU to figure out the exact features. 80 // Use CPU to figure out the exact features. 88 // Use CPU to figure out the exact features. 91 // v7 CPUs have lots of different feature sets. If no CPU is specified, 93 // the "minimum" feature set and use CPU string to figure out the exact 99 // Use CPU to figure out the exact features. 140 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, [all...] |
/external/llvm/include/llvm/Support/ |
TargetRegistry.h | 94 StringRef CPU, 98 StringRef CPU, 108 StringRef CPU); 345 /// \param CPU This specifies the name of the target CPU. 348 MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, 352 return MCSubtargetInfoCtorFn(Triple, CPU, Features); 362 TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, 369 return TargetMachineCtorFn(*this, Triple, CPU, Features, Options, 376 MCAsmBackend *createMCAsmBackend(StringRef Triple, StringRef CPU) const [all...] |
/external/chromium_org/third_party/WebKit/Source/core/platform/image-decoders/bmp/ |
BMPImageReader.h | 36 #include "wtf/CPU.h" 51 #if CPU(BIG_ENDIAN) 61 #if CPU(BIG_ENDIAN) 210 #if CPU(BIG_ENDIAN)
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/external/chromium_org/v8/src/ia32/ |
assembler-ia32-inl.h | 42 #include "cpu.h" 57 CPU::FlushICache(p, sizeof(uint32_t)); 62 CPU::FlushICache(p, sizeof(uint32_t)); 69 CPU::FlushICache(p, sizeof(uint32_t)); 75 CPU::FlushICache(p, sizeof(uint32_t)); 80 CPU::FlushICache(p, sizeof(uint32_t)); 137 CPU::FlushICache(pc_, sizeof(Address)); 183 CPU::FlushICache(pc_, sizeof(Address)); 258 CPU::FlushICache(pc_, sizeof(Address)); 265 CPU::FlushICache(pc_, sizeof(Address)) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMSubtarget.h | 181 /// CPUString - String name of used CPU. 205 ARMSubtarget(const std::string &TT, const std::string &CPU, 217 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 223 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
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/external/llvm/lib/Target/Hexagon/ |
HexagonTargetMachine.cpp | 68 StringRef CPU, StringRef FS, 73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 77 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
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/external/llvm/lib/Target/R600/ |
AMDGPUTargetMachine.cpp | 52 StringRef CPU, StringRef FS, 58 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel), 59 Subtarget(TT, CPU, FS),
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/frameworks/compile/slang/ |
slang.cpp | 178 void Slang::createTarget(const std::string &Triple, const std::string &CPU, 185 if (!CPU.empty()) 186 mTargetOpts->CPU = CPU; 270 void Slang::init(const std::string &Triple, const std::string &CPU, 283 createTarget(Triple, CPU, Features);
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/external/llvm/lib/Target/Mips/ |
MipsSubtarget.h | 144 MipsSubtarget(const std::string &TT, const std::string &CPU, 150 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/external/llvm/lib/Target/X86/ |
X86Subtarget.cpp | 369 "target-cpu"); 372 std::string CPU = 378 resetSubtargetFeatures(CPU, FS); 382 void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { 383 std::string CPUName = CPU; 384 if (!FS.empty() || !CPU.empty()) { 430 // CPUName may have been set by the CPU detection code. Make sure the 501 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, 504 : X86GenSubtargetInfo(TT, CPU, FS) 511 resetSubtargetFeatures(CPU, FS) [all...] |
/external/srec/srec/include/ |
sample.h | 56 #if !(defined(__vxworks) && (CPU & SIMNT)) 64 #if !(defined(__vxworks) && (CPU & SIMNT))
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/external/chromium_org/v8/src/x64/ |
assembler-x64-inl.h | 33 #include "cpu.h" 216 CPU::FlushICache(pc, sizeof(int32_t)); 243 CPU::FlushICache(pc_, sizeof(Address)); 246 CPU::FlushICache(pc_, sizeof(int32_t)); 251 CPU::FlushICache(p, sizeof(uint32_t)); 323 CPU::FlushICache(pc_, sizeof(Address)); 363 CPU::FlushICache(pc_, sizeof(Address)); 423 CPU::FlushICache(pc_ + Assembler::kRealPatchReturnSequenceAddressOffset, 455 CPU::FlushICache(pc_, sizeof(Address)); 462 CPU::FlushICache(pc_, sizeof(Address)) [all...] |
/external/v8/src/x64/ |
assembler-x64-inl.h | 33 #include "cpu.h" 195 CPU::FlushICache(pc, sizeof(int32_t)); 210 CPU::FlushICache(pc_, sizeof(Address)); 213 CPU::FlushICache(pc_, sizeof(int32_t)); 256 CPU::FlushICache(pc_, sizeof(Address)); 292 CPU::FlushICache(pc_, sizeof(Address)); 324 CPU::FlushICache(pc_, sizeof(Address)); 368 CPU::FlushICache(pc_ + Assembler::kRealPatchReturnSequenceAddressOffset, 400 CPU::FlushICache(pc_, sizeof(Address)); 407 CPU::FlushICache(pc_, sizeof(Address)) [all...] |
/external/oprofile/events/x86-64/family10/ |
unit_masks | 135 0x01 GART aperture hit on access from CPU 147 0xa4 Requests Local CPU to Local I/O 148 0xa5 Requests Local (CPU or I/O) to Local I/O 149 0xa8 Requests Local CPU to Local Memory 150 0xaa Requests Local (CPU or I/O) to Local Memory 151 0xac Requests Local CPU to Local (I/O or Mem) 152 0xaf Requests Local (CPU or I/O) to Local (I/O or Mem) 156 0x94 Requests Local CPU to Remote I/O 157 0x95 Requests Local (CPU or I/O) to Remote I/O 158 0x98 Requests Local CPU to Remote Memor [all...] |
/build/core/combo/arch/x86/ |
x86.mk | 3 # which mandates specific CPU extensions to be available. 7 # the host development machine's CPU).
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