| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| r200_blit.c | 102 struct radeon_bo *bo,
152 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
154 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
292 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
298 struct radeon_bo *bo,
335 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
337 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
351 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
353 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
516 "offset [%d x %d], format %s, bo %p\n"
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/ |
| nv50_miptree.c | 117 nouveau_bo_ref(NULL, &mt->base.bo);
133 if (!mt || !mt->base.bo)
139 mt->base.bo,
293 &mt->base.bo);
299 mt->base.address = mt->base.bo->offset;
324 mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride);
325 if (mt->base.bo == NULL) {
330 mt->base.address = mt->base.bo->offset;
338 mt->level[0].tile_mode = mt->base.bo->config.nv50.tile_mode;
340 /* no need to adjust bo reference count *
[all...] |
| nv50_screen.h | 62 struct nouveau_bo *bo; member in struct:nv50_screen::__anon24915
98 if (likely(res->bo)) {
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_blit.c | 102 struct radeon_bo *bo,
152 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
154 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
292 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
298 struct radeon_bo *bo,
335 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
337 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
351 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
353 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
516 "offset [%d x %d], format %s, bo %p\n"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
| radeonsi_pm4.c | 89 struct si_resource *bo,
95 si_resource_reference(&state->bo[idx], bo);
169 si_resource_reference(&state->bo[i], NULL);
209 r600_context_bo_reloc(rctx, state->bo[i],
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_sf_state.c | 145 drm_intel_bo *bo = intel->batch.bo; local
193 sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
306 drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
308 intel->batch.bo, (brw->sf.vp_offset |
|
| gen7_sol_state.c | 58 drm_intel_bo *bo; local
76 bo = intel_bufferobj_buffer(intel, bufferobj, INTEL_WRITE_PART);
82 assert(end <= bo->size);
94 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
95 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
|
| brw_vtbl.c | 58 dri_bo_release(drm_intel_bo **bo)
60 drm_intel_bo_unreference(*bo);
61 *bo = NULL;
202 /* Mark that the current program cache BO has been used by the GPU.
|
| gen7_misc_state.c | 198 OUT_RELOC(region->bo,
224 OUT_RELOC(hiz_mt->region->bo,
266 OUT_RELOC(stencil_mt->region->bo,
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/nouveau/ |
| nouveau_texture.c | 91 if (s->bo) {
93 nouveau_pushbuf_refd(context_push(ctx), s->bo)) {
110 &st->bo, &st->offset);
120 if (!s->bo->map) {
121 ret = nouveau_bo_map(s->bo, flags, client);
125 nti->base.Map = s->bo->map +
140 if (st->bo) {
168 if (s->bo) {
170 nouveau_pushbuf_refd(context_push(ctx), s->bo)) {
187 &st->bo, &st->offset)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_maos_arrays.c | 101 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32);
106 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32);
115 radeon_bo_map(aos->bo, 1);
116 out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
135 radeon_bo_unmap(aos->bo);
|
| radeon_maos_verts.c | 376 rmesa->radeon.tcl.aos[0].bo)
379 if (rmesa->radeon.tcl.aos[0].bo)
383 &rmesa->radeon.tcl.aos[0].bo,
422 radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1);
424 rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
425 radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo);
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| radeonsi_pm4.c | 89 struct si_resource *bo,
95 si_resource_reference(&state->bo[idx], bo);
169 si_resource_reference(&state->bo[i], NULL);
209 r600_context_bo_reloc(rctx, state->bo[i],
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_sf_state.c | 145 drm_intel_bo *bo = intel->batch.bo; local
193 sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
306 drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
308 intel->batch.bo, (brw->sf.vp_offset |
|
| gen7_sol_state.c | 58 drm_intel_bo *bo; local
76 bo = intel_bufferobj_buffer(intel, bufferobj, INTEL_WRITE_PART);
82 assert(end <= bo->size);
94 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
95 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
|
| brw_vtbl.c | 58 dri_bo_release(drm_intel_bo **bo)
60 drm_intel_bo_unreference(*bo);
61 *bo = NULL;
202 /* Mark that the current program cache BO has been used by the GPU.
|
| gen7_misc_state.c | 198 OUT_RELOC(region->bo,
224 OUT_RELOC(hiz_mt->region->bo,
266 OUT_RELOC(stencil_mt->region->bo,
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nouveau_texture.c | 91 if (s->bo) {
93 nouveau_pushbuf_refd(context_push(ctx), s->bo)) {
110 &st->bo, &st->offset);
120 if (!s->bo->map) {
121 ret = nouveau_bo_map(s->bo, flags, client);
125 nti->base.Map = s->bo->map +
140 if (st->bo) {
168 if (s->bo) {
170 nouveau_pushbuf_refd(context_push(ctx), s->bo)) {
187 &st->bo, &st->offset)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_maos_arrays.c | 101 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32);
106 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32);
115 radeon_bo_map(aos->bo, 1);
116 out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
135 radeon_bo_unmap(aos->bo);
|
| radeon_maos_verts.c | 376 rmesa->radeon.tcl.aos[0].bo)
379 if (rmesa->radeon.tcl.aos[0].bo)
383 &rmesa->radeon.tcl.aos[0].bo,
422 radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1);
424 rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
425 radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo);
|
| /frameworks/native/opengl/libagl/ |
| array.cpp | 314 const GLvoid *pointer, const buffer_t* bo, GLsizei count)
333 this->bo = bo;
339 physical_pointer = (bo) ? (bo->data + uintptr_t(pointer)) : pointer;
1458 buffer_t const* bo = 0; local
1485 buffer_t const* bo = ((target == GL_ARRAY_BUFFER) ? local
1515 buffer_t const* bo = ((target == GL_ARRAY_BUFFER) ? local
[all...] |
| /frameworks/opt/telephony/src/java/com/android/internal/telephony/gsm/ |
| SmsMessage.java | 272 ByteArrayOutputStream bo = getSubmitPduHead( local
320 bo.write(0x00);
329 bo.write(0x08);
333 bo.write(userData, 0, userData.length);
334 ret.encodedMessage = bo.toByteArray();
414 ByteArrayOutputStream bo = getSubmitPduHead( local
421 bo.write(0x04);
426 bo.write(data.length + smsHeaderData.length + 1);
429 bo.write(smsHeaderData.length);
430 bo.write(smsHeaderData, 0, smsHeaderData.length)
454 ByteArrayOutputStream bo = new ByteArrayOutputStream( local
[all...] |
| /external/chromium_org/third_party/flot/ |
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[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/ |
| nv50_screen.h | 62 struct nouveau_bo *bo; member in struct:nv50_screen::__anon14573
98 if (likely(res->bo)) {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/ |
| nvc0_screen.h | 57 struct nouveau_bo *bo; member in struct:nvc0_screen::__anon14583
97 if (likely(res->bo)) {
|
