| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| gen-fma-test.py | 3 def emit(opcode,suffix,width,order,optype):
5 d['opcode']=opcode
29 print "v%(opcode)s%(order)s%(suffix)s %(op1)s, %(op2)s, %(op3)s" % (d)
32 print "v%(opcode)s%(order)s%(suffix)s %(op1)s, %(op2)s, %(op3)s" % (d)
35 for opcode in opcodes:
39 emit(opcode,suffix,width,order,optype)
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_swizzle.h | 44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
|
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| SparseSwitchPayloadDecodedInstruction.java | 38 int opcode, int[] keys, int[] targets) {
39 super(format, opcode, 0, null, 0, 0L);
|
| ZeroRegisterDecodedInstruction.java | 28 public ZeroRegisterDecodedInstruction(InstructionCodec format, int opcode,
30 super(format, opcode, index, indexType, target, literal);
|
| /dalvik/vm/compiler/template/mips/ |
| TEMPLATE_FLOAT_TO_INT_VFP.S | 14 bgez t0, .L${opcode}_set_vreg
22 blez t0, .L${opcode}_set_vreg
29 bnez t0, .L${opcode}_set_vreg
33 b .L${opcode}_set_vreg
38 bc1t .L${opcode}_set_vreg_f
43 bc1t .L${opcode}_set_vreg_f
48 bc1t .L${opcode}_set_vreg_f
51 b .L${opcode}_set_vreg_f
|
| /dalvik/vm/mterp/c/ |
| OP_MOVE_RESULT.cpp | 1 HANDLE_OPCODE($opcode /*vAA*/)
|
| /dalvik/vm/mterp/mips/ |
| OP_FLOAT_TO_INT.S | 15 bgez t0, .L${opcode}_set_vreg
23 blez t0, .L${opcode}_set_vreg
30 bnez t0, .L${opcode}_set_vreg
34 b .L${opcode}_set_vreg
39 bc1t .L${opcode}_set_vreg_f
44 bc1t .L${opcode}_set_vreg_f
49 bc1t .L${opcode}_set_vreg_f
52 b .L${opcode}_set_vreg_f
|
| OP_CHECK_CAST.S | 18 beqz rOBJ, .L${opcode}_okay # null obj, cast always succeeds
22 beqz a1, .L${opcode}_resolve # not resolved, do it now
23 .L${opcode}_resolved:
25 bne a0, a1, .L${opcode}_fullcheck # no, do full check
26 .L${opcode}_okay:
28 GET_INST_OPCODE(t0) # extract opcode from rINST
37 .L${opcode}_fullcheck:
41 bnez v0, .L${opcode}_okay # no, success
42 b .L${opcode}_castfailure
45 .L${opcode}_castfailure
[all...] |
| unflop.S | 22 .L${opcode}_set_vreg:
27 .L${opcode}_set_vreg_f:
30 GET_INST_OPCODE(t1) # extract opcode from rINST
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_shader.h | 32 uint32_t brw_math_function(enum opcode op);
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| SparseSwitchPayloadDecodedInstruction.java | 38 int opcode, int[] keys, int[] targets) {
39 super(format, opcode, 0, null, 0, 0L);
|
| ZeroRegisterDecodedInstruction.java | 28 public ZeroRegisterDecodedInstruction(InstructionCodec format, int opcode,
30 super(format, opcode, index, indexType, target, literal);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_shader.h | 32 uint32_t brw_math_function(enum opcode op);
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction21t.java | 33 import org.jf.dexlib.Code.Opcode;
44 public Instruction21t(Opcode opcode, short regA, short offB) {
45 super(opcode);
59 private Instruction21t(Opcode opcode, byte[] buffer, int bufferIndex) {
60 super(opcode);
62 assert buffer[bufferIndex] == opcode.value;
70 out.writeByte(opcode.value);
99 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex)
[all...] |
| Instruction22t.java | 33 import org.jf.dexlib.Code.Opcode;
45 public Instruction22t(Opcode opcode, byte regA, byte regB, short offC) {
46 super(opcode);
62 private Instruction22t(Opcode opcode, byte[] buffer, int bufferIndex) {
63 super(opcode);
65 assert buffer[bufferIndex] == opcode.value;
75 out.writeByte(opcode.value);
108 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex)
[all...] |
| /sdk/emulator/qtools/ |
| armdis.h | 7 #include "opcode.h"
12 static Opcode decode(uint32_t insn);
15 static Opcode decode00(uint32_t insn);
16 static Opcode decode01(uint32_t insn);
17 static Opcode decode10(uint32_t insn);
18 static Opcode decode11(uint32_t insn);
19 static Opcode decode_mul(uint32_t insn);
20 static Opcode decode_ldrh(uint32_t insn);
21 static Opcode decode_alu(uint32_t insn);
23 static char *disasm_alu(Opcode opcode, uint32_t insn, char *ptr)
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 57 res->opcode = kMipsFmovd;
61 res->opcode = kMipsFmovs;
64 res->opcode = kMipsMtc1;
70 res->opcode = kMipsMfc1;
158 MipsOpCode opcode = kMipsNop; local
161 opcode = kMipsB;
167 res = newLIR0(cUnit, opcode);
188 MipsOpCode opcode = kMipsNop; local
191 opcode = kMipsJalr;
196 return newLIR2(cUnit, opcode, r_RA, rDestSrc)
208 MipsOpCode opcode = kMipsNop; local
237 MipsOpCode opcode = kMipsNop; local
278 MipsOpCode opcode = kMipsNop; local
368 MipsOpCode opcode = kMipsNop; local
426 MipsOpCode opcode = kMipsNop; local
488 MipsOpCode opcode = kMipsNop; local
607 MipsOpCode opcode = kMipsNop; local
725 MipsOpCode opcode = kMipsNop; local
838 MipsOpCode opcode; local
[all...] |
| /dalvik/vm/mterp/x86/ |
| bindivLit8.S | 14 jne .L${opcode}_continue_div
16 jne .L${opcode}_continue_div
24 .L${opcode}_continue_div:
|
| /external/chromium_org/third_party/mesa/src/src/gallium/docs/source/exts/ |
| formatting.py | 20 opcode, desc = sig.split("-", 1)
21 opcode = opcode.strip().upper()
23 signode += sphinx.addnodes.desc_name(opcode, opcode)
25 return opcode
30 app.add_description_unit("opcode", "opcode", "%s (TGSI opcode)",
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /external/mesa3d/src/gallium/docs/source/exts/ |
| formatting.py | 20 opcode, desc = sig.split("-", 1)
21 opcode = opcode.strip().upper()
23 signode += sphinx.addnodes.desc_name(opcode, opcode)
25 return opcode
30 app.add_description_unit("opcode", "opcode", "%s (TGSI opcode)",
|
| /external/proguard/src/proguard/optimize/peephole/ |
| GotoGotoReplacer.java | 78 byte opcode = branchInstruction.opcode;
79 if (opcode == InstructionConstants.OP_GOTO ||
80 opcode == InstructionConstants.OP_GOTO_W)
94 if (targetInstruction.opcode == InstructionConstants.OP_GOTO)
100 new BranchInstruction(opcode,
|
| GotoReturnReplacer.java | 78 byte opcode = branchInstruction.opcode;
79 if (opcode == InstructionConstants.OP_GOTO ||
80 opcode == InstructionConstants.OP_GOTO_W)
90 switch (targetInstruction.opcode)
100 new SimpleInstruction(targetInstruction.opcode);
|
