| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | [all...] |
| SelectionDAGISel.cpp | 471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
472 if ((MCID.isCall() && !MCID.isReturn()) ||
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 577 const MCInstrDesc &MCID = TII.get(ADDriOpc);
578 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
580 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| ARMBaseInstrInfo.cpp | 151 const MCInstrDesc &MCID = MI->getDesc();
152 unsigned NumOps = MCID.getNumOperands();
548 const MCInstrDesc &MCID = MI->getDesc();
549 if (MCID.getSize())
550 return MCID.getSize();
602 unsigned NumOps = MCID.getNumOperands();
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMFastISel.cpp | 253 const MCInstrDesc &MCID = MI->getDesc();
256 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
260 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
261 if (MCID.OpInfo[i].isPredicate())
[all...] |
| ARMISelLowering.cpp | [all...] |
| ARMISelDAGToDAG.cpp | 439 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
440 if (MCID.mayStore())
442 unsigned Opcode = MCID.getOpcode();
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 802 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| ExecutionDepsFix.cpp | 455 const MCInstrDesc &MCID = MI->getDesc();
457 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
| MachineFunction.cpp | 173 MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
176 MachineInstr(*this, MCID, DL, NoImp);
[all...] |
| RegisterCoalescer.cpp | 765 const MCInstrDesc &MCID = DefMI->getDesc();
766 if (MCID.getNumDefs() != 1)
774 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFunction.h | 374 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 551 const MCInstrDesc &MCID = MI.getDesc();
556 if (MCID.getSize())
557 return MCID.getSize();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 813 const MCInstrDesc &MCID = TII.get(ADDriOpc);
815 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
817 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| PPCInstrInfo.cpp | 550 const MCInstrDesc &MCID = get(Opc);
551 if (MCID.getNumOperands() == 3)
552 BuildMI(MBB, I, DL, MCID, DestReg)
555 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 553 const MCInstrDesc& MCID = PacketMI->getDesc();
556 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
[all...] |
| HexagonISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
