| /external/llvm/lib/CodeGen/ |
| RegAllocBase.cpp | 111 MachineInstr *MI;
113 (MI = I.skipInstruction());)
114 if (MI->isInlineAsm())
116 if (MI)
117 MI->emitError(Msg);
|
| TailDuplication.cpp | 86 void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
92 void DuplicateInstruction(MachineInstr *MI,
152 MachineBasicBlock::iterator MI = MBB->begin();
153 while (MI != MBB->end()) {
154 if (!MI->isPHI())
160 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
161 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
168 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
175 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
176 MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB()
[all...] |
| VirtRegMap.cpp | 273 MachineInstr *MI = MII;
276 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
277 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
327 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
330 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
333 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
335 DEBUG(dbgs() << "> " << *MI);
338 if (MI->isIdentityCopy()) {
340 if (MI->getNumOperands() == 2) {
343 Indexes->removeMachineInstrFromMaps(MI);
[all...] |
| PostRASchedulerList.cpp | 162 void Observe(MachineInstr *MI, unsigned Count);
183 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
314 MachineInstr *MI = llvm::prior(I);
318 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
323 Current = MI;
325 Scheduler.Observe(MI, CurrentCount);
327 I = MI;
329 if (MI->isBundle())
330 Count -= MI->getBundleSize()
[all...] |
| ScheduleDAGInstrs.cpp | 41 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
43 cl::desc("Enable use of AA during MI GAD construction"));
125 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
128 if (!MI->hasOneMemOperand() ||
129 !(*MI->memoperands_begin())->getValue() ||
130 (*MI->memoperands_begin())->isVolatile())
133 const Value *V = (*MI->memoperands_begin())->getValue();
288 const MachineInstr *MI = SU->getInstr();
289 const MachineOperand &MO = MI->getOperand(OperIdx);
314 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()))
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 109 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
110 OutMI.setOpcode(MI->getOpcode());
112 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
113 const MachineOperand &MO = MI->getOperand(i);
118 MI->dump();
|
| MSP430RegisterInfo.cpp | 109 MachineInstr &MI = *II;
110 MachineBasicBlock &MBB = *MI.getParent();
113 DebugLoc dl = MI.getDebugLoc();
114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
128 Offset += MI.getOperand(FIOperandNum + 1).getImm();
130 if (MI.getOpcode() == MSP430::ADD16ri) {
136 MI.setDesc(TII.get(MSP430::MOV16rr));
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
143 unsigned DstReg = MI.getOperand(0).getReg();
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false)
[all...] |
| MSP430FrameLowering.cpp | 97 MachineInstr *MI =
101 MI->getOperand(3).setIsDead();
159 MachineInstr *MI =
164 MI->getOperand(3).setIsDead();
169 MachineInstr *MI =
173 MI->getOperand(3).setIsDead();
181 MachineBasicBlock::iterator MI,
188 if (MI != MBB.end()) DL = MI->getDebugLoc();
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 42 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
44 if (MI->getOpcode() == SP::LDri ||
45 MI->getOpcode() == SP::LDXri ||
46 MI->getOpcode() == SP::LDFri ||
47 MI->getOpcode() == SP::LDDFri) {
48 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
49 MI->getOperand(2).getImm() == 0) {
50 FrameIndex = MI->getOperand(1).getIndex();
51 return MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 79 virtual void EmitInstruction(const MachineInstr *MI);
81 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
83 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
86 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
139 void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
141 const MachineOperand &MO = MI->getOperand(OpNo);
237 bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
247 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
252 if (!MI->getOperand(OpNo).isReg() ||
253 OpNo+1 == MI->getNumOperands() |
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 57 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
58 int Opcode = MI->getOpcode();
61 if ((MI->getOperand(1).isFI()) && // is a stack slot
62 (MI->getOperand(2).isImm()) && // the imm is zero
63 (isZeroImm(MI->getOperand(2))))
65 FrameIndex = MI->getOperand(1).getIndex();
66 return MI->getOperand(0).getReg();
78 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
80 int Opcode = MI->getOpcode();
83 if ((MI->getOperand(1).isFI()) && // is a stack slo
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 200 isPhysicalRegCopy(MachineInstr *MI) {
201 if (MI->getOpcode() != AMDGPU::COPY)
204 return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
252 MachineInstr *MI = SU->getInstr();
254 if (TII->isTransOnly(MI))
257 switch (MI->getOpcode()) {
266 if (MI->getOperand(1).isUndef()) {
267 // MI will become a KILL, don't considers it in scheduling
277 if(TII->isVector(*MI) ||
278 TII->isCubeOp(MI->getOpcode()) |
[all...] |
| SIFixSGPRCopies.cpp | 140 MachineInstr &MI = *I;
141 if (MI.getOpcode() != AMDGPU::PHI) {
144 unsigned Reg = MI.getOperand(0).getReg();
|
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 310 // If starting offset isn't zero, insert a MI to materialize a new base.
515 static bool definesCPSR(MachineInstr *MI) {
516 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
517 const MachineOperand &MO = MI->getOperand(i);
529 static bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
533 if (!MI)
537 switch (MI->getOpcode()) {
551 unsigned Scale = (MI->getOpcode() == ARM::tSUBspi) ? 4 : 1; // FIXME
552 if (!(MI->getOperand(0).getReg() == Base &&
553 MI->getOperand(1).getReg() == Base &
[all...] |
| Thumb1FrameLowering.cpp | 223 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
224 if (MI->getOpcode() == ARM::tLDRspi &&
225 MI->getOperand(1).isFI() &&
226 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
228 else if (MI->getOpcode() == ARM::tPOP) {
231 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
232 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
332 MachineBasicBlock::iterator MI,
342 if (MI != MBB.end()) DL = MI->getDebugLoc()
[all...] |
| ARMFrameLowering.cpp | 36 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
92 static bool isCSRestore(MachineInstr *MI,
96 if (MI->getOpcode() == ARM::LDMIA_RET ||
97 MI->getOpcode() == ARM::t2LDMIA_RET ||
98 MI->getOpcode() == ARM::LDMIA_UPD ||
99 MI->getOpcode() == ARM::t2LDMIA_UPD ||
100 MI->getOpcode() == ARM::VLDMDIA_UPD) {
103 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
104 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
108 if ((MI->getOpcode() == ARM::LDR_POST_IMM |
[all...] |
| /external/clang/lib/Lex/ |
| PPDirectives.cpp | 52 return &(MIChain->MI);
56 MacroInfo *MI = AllocateMacroInfo();
57 new (MI) MacroInfo(L);
58 return MI;
70 MacroInfo *MI = &MIChain->MI;
71 new (MI) MacroInfo(L);
72 MI->FromASTFile = true;
73 MI->setOwningModuleID(SubModuleID);
74 return MI;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LexicalScopes.h | 180 /// openInsnRange - This scope covers instruction range starting from MI.
181 void openInsnRange(const MachineInstr *MI) {
183 FirstInsn = MI;
186 Parent->openInsnRange(MI);
191 void extendInsnRange(const MachineInstr *MI) {
192 assert (FirstInsn && "MI Range is not open!");
193 LastInsn = MI;
195 Parent->extendInsnRange(MI);
|
| ScheduleDAGInstrs.h | 173 SUnit *newSUnit(MachineInstr *MI);
175 /// getSUnit - Return an existing SUnit for this MI, or NULL.
176 SUnit *getSUnit(MachineInstr *MI) const;
234 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
238 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
245 /// getSUnit - Return an existing SUnit for this MI, or NULL.
246 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
247 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 137 MachineBasicBlock::iterator MI,
148 MachineBasicBlock::iterator MI,
216 MachineBasicBlock::iterator MI) const {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 102 MachineInstr* MI = *i;
103 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
106 MachineOperand& MO = MI->getOperand(2);
224 MachineBasicBlock::iterator MI,
259 TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
267 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
278 MachineBasicBlock::iterator MI,
313 TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(),
321 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
331 MachineInstr &MI = *I
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPURegisterInfo.h | 54 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
| /external/clang/include/clang/Serialization/ |
| ASTDeserializationListener.h | 42 virtual void MacroRead(serialization::MacroID ID, MacroInfo *MI) { }
|
