| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
81 switch (MI->getOperand(0).getImm()) {
89 printInstruction(MI, O);
93 printPredicateOperand(MI, 1, O);
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
109 printSBitModifierOperand(MI, 6, O)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 68 bool isTriviallyReMaterializable(const MachineInstr *MI,
70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
71 (MI->getDesc().isRematerializable() &&
72 (isReallyTriviallyReMaterializable(MI, AA) ||
73 isReallyTriviallyReMaterializableGeneric(MI, AA)));
83 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
94 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
113 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
124 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
132 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 94 bool removeKill(MachineInstr *MI) {
96 I = std::find(Kills.begin(), Kills.end(), MI);
146 // DistanceMap - Keep track the distance of a MI from the start of the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
184 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
198 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
200 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound)
[all...] |
| MachineInstrBuilder.h | 47 MachineInstr *MI;
49 MachineInstrBuilder() : MF(0), MI(0) {}
53 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
57 operator MachineInstr*() const { return MI; }
58 MachineInstr *operator->() const { return MI; }
59 operator MachineBasicBlock::iterator() const { return MI; }
68 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
84 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
94 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val))
[all...] |
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.h | 28 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
31 void printInstruction(const MCInst *MI, raw_ostream &O);
34 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
36 void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
39 void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
| MSP430InstPrinter.cpp | 28 void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
30 printInstruction(MI, O);
34 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
36 const MCOperand &Op = MI->getOperand(OpNo);
45 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
48 const MCOperand &Op = MI->getOperand(OpNo);
59 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
62 const MCOperand &Base = MI->getOperand(OpNo);
63 const MCOperand &Disp = MI->getOperand(OpNo+1);
88 void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo
[all...] |
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.h | 31 void printInstruction(const MCInst *MI, raw_ostream &O);
35 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
37 void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O);
38 void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O);
39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 65 bool runOnInstruction(MachineInstr *MI);
105 bool hasPartialWrite(MachineInstr *MI);
106 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
113 MachineInstr *elideCopies(MachineInstr *MI);
114 void elideCopiesAndPHIs(MachineInstr *MI,
120 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
121 unsigned optimizeSDPattern(MachineInstr *MI);
127 void eraseInstrWithNoUses(MachineInstr *MI);
164 MachineInstr *MI = MRI->getVRegDef(SReg);
165 if (!MI) return ARM::ssub_0
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
109 unsigned getEncodingType(const MCInst &MI) const;
112 unsigned getEncodingBytes(const MCInst &MI) const
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
109 unsigned getEncodingType(const MCInst &MI) const;
112 unsigned getEncodingBytes(const MCInst &MI) const
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.h | 24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
123 MachineBasicBlock::iterator MI,
133 MachineBasicBlock::iterator MI,
142 MachineInstr *MI,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.h | 18 void printInstruction(const MCInst *MI, raw_ostream &O);
22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O);
27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 115 bool optimizeBitcastInstr(MachineInstr *MI, MachineBasicBlock *MBB);
116 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
117 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
119 bool optimizeSelect(MachineInstr *MI);
120 bool isMoveImmediate(MachineInstr *MI,
123 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
126 bool isLoadFoldable(MachineInstr *MI, unsigned &FoldAsLoadDefReg);
148 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
197 if (UseMI == MI)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUMCInstLower.cpp | 33 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
34 OutMI.setOpcode(MI->getOpcode());
36 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
37 const MachineOperand &MO = MI->getOperand(i);
64 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
67 if (MI->isBundle()) {
68 const MachineBasicBlock *MBB = MI->getParent();
69 MachineBasicBlock::const_instr_iterator I = MI;
80 MCInstLowering.lower(MI, TmpInst);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.h | 21 void EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
|
| X86IntelInstPrinter.cpp | 34 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
42 printInstruction(MI, OS);
49 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
52 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
76 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
118 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
120 const MCOperand &Op = MI->getOperand(OpNo)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.h | 24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
123 MachineBasicBlock::iterator MI,
133 MachineBasicBlock::iterator MI,
142 MachineInstr *MI,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.h | 18 void printInstruction(const MCInst *MI, raw_ostream &O);
22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O);
27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 47 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
51 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
90 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
93 if (MI.getOpcode() == AMDGPU::RETURN ||
94 MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
95 MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
96 MI.getOpcode() == AMDGPU::BUNDLE ||
97 MI.getOpcode() == AMDGPU::KILL) {
100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 53 AArch64InstPrinter::printOffsetSImm9Operand(const MCInst *MI,
55 const MCOperand &MOImm = MI->getOperand(OpNum);
62 AArch64InstPrinter::printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
65 unsigned ExtImm = MI->getOperand(OpNum).getImm();
92 AArch64InstPrinter::printAddSubImmLSL0Operand(const MCInst *MI,
94 const MCOperand &Imm12Op = MI->getOperand(OpNum);
107 AArch64InstPrinter::printAddSubImmLSL12Operand(const MCInst *MI, unsigned OpNum,
110 printAddSubImmLSL0Operand(MI, OpNum, O);
116 AArch64InstPrinter::printBareImmOperand(const MCInst *MI, unsigned OpNum,
118 const MCOperand &MO = MI->getOperand(OpNum)
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 85 void printInstruction(const MCInst *MI, raw_ostream &O);
89 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
91 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
94 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
95 void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O);
96 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
97 void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
98 void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
100 bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
102 bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 57 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
62 MachineBasicBlock &MBB = *MI->getParent();
67 DebugLoc DL = MI->getDebugLoc();
70 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
73 MI->getOperand(FIOperandNum + 1).getImm());
76 if (MI->isDebugValue()) {
77 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
78 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
84 unsigned Opcode = MI->getOpcode();
87 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 69 uint64_t getBinaryCodeForInstr(const MCInst &MI,
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx
[all...] |
