| /external/llvm/lib/MC/ |
| MCInst.cpp | 43 OS << "<MCInst " << getOpcode();
54 OS << "<MCInst #" << getOpcode();
58 OS << ' ' << Printer->getOpcodeName(getOpcode());
|
| /external/llvm/unittests/Transforms/Utils/ |
| IntegerDivision.cpp | 41 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
46 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
49 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub);
71 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv);
76 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp);
79 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI);
101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
106 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
109 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub);
131 EXPECT_TRUE(BB->front().getOpcode() == Instruction::URem)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600Packetizer.cpp | 72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
80 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
83 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
92 if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
93 BI->getOpcode() == AMDGPU::DOT4_eg) {
130 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
160 if (!TII->isALUInstr(MI->getOpcode()))
162 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
166 if (TII->isLDSInstr(MI->getOpcode()))
178 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 89 switch (MI.getOpcode()) {
133 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
180 if (LastInst->getOpcode() == NVPTX::GOTO) {
183 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
201 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
202 LastInst->getOpcode() == NVPTX::GOTO) {
211 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
212 LastInst->getOpcode() == NVPTX::GOTO) {
229 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch
[all...] |
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
93 if (MI.getOpcode() == AMDGPU::RETURN ||
94 MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
95 MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
96 MI.getOpcode() == AMDGPU::BUNDLE ||
97 MI.getOpcode() == AMDGPU::KILL) {
174 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 145 inline unsigned getOpcode() const;
365 /// getOpcode - Return the SelectionDAG opcode value for this node. For
369 unsigned getOpcode() const { return (unsigned short)NodeType; }
838 inline unsigned SDValue::getOpcode() const {
839 return Node->getOpcode();
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 112 switch (I->getOpcode()) {
121 return TTI->getCFInstrCost(I->getOpcode());
145 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK,
151 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy);
156 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy);
161 return TTI->getMemoryOpCost(I->getOpcode(), ValTy,
167 return TTI->getMemoryOpCost(I->getOpcode(), I->getType(),
184 return TTI->getCastInstrCost(I->getOpcode(), I->getType(), SrcTy);
192 return TTI->getVectorInstrCost(I->getOpcode(),
201 return TTI->getVectorInstrCost(I->getOpcode(),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 93 switch(MI->getOpcode()) {
101 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
102 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
106 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
137 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) {
142 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) {
158 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) {
163 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) {
186 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) {
195 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f )
[all...] |
| HexagonCFGOptimizer.cpp | 76 switch(MI->getOpcode()) {
113 int Opc = MI->getOpcode();
165 if ((MI->getOpcode() == Hexagon::JMP_t) ||
166 (MI->getOpcode() == Hexagon::JMP_f)) {
178 IsUnconditionalJump(LayoutSucc->front().getOpcode())) {
185 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 106 switch (I->getOpcode()) {
201 switch (I->getOpcode()) {
314 bool isLeftShift = I.getOpcode() == Instruction::Shl;
319 if (I.getOpcode() != Instruction::AShr &&
337 if (I.getOpcode() != Instruction::AShr)
346 if (BO->getOpcode() == Instruction::Mul && isLeftShift)
372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
386 if (I.getOpcode() == Instruction::Shl)
389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
408 switch (Op0BO->getOpcode()) {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
80 int Opcode = MI->getOpcode();
209 if (IsBRU(LastInst->getOpcode())) {
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
235 unsigned SecondLastOpc = SecondLastInst->getOpcode();
241 && IsBRU(LastInst->getOpcode())) {
253 if (IsBRU(SecondLastInst->getOpcode()) &&
254 IsBRU(LastInst->getOpcode())) {
263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 111 (MI->getOpcode() == SP::RESTORErr
112 || MI->getOpcode() == SP::RESTOREri)) {
159 if (slot->getOpcode() == SP::RET)
162 if (slot->getOpcode() == SP::RETL) {
166 if (J->getOpcode() == SP::RESTORErr
167 || J->getOpcode() == SP::RESTOREri) {
265 switch(MI->getOpcode()) {
304 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
328 if (candidate->getOpcode() == SP::UNIMP)
340 switch (I->getOpcode()) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| /dalvik/dx/src/com/android/dx/merge/ |
| InstructionTransformer.java | 70 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
80 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
90 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
100 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 103 if (Addr.getOpcode() == ISD::FrameIndex) {
111 } else if (Addr.getOpcode() == ISD::ADD) {
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
123 Addr.getOpcode() == ISD::TargetGlobalAddress) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
136 if (Addr.getOpcode() == ISD::FrameIndex) {
144 } else if (Addr.getOpcode() == ISD::ADD) {
155 unsigned int Opc = N->getOpcode();
320 if (Addr.getOpcode() == ISD::TargetExternalSymbol |
[all...] |
| R600ExpandSpecialInstrs.cpp | 63 bool IsReduction = TII->isReductionOp(MI.getOpcode());
65 bool IsCube = TII->isCubeOp(MI.getOpcode());
135 switch (MI.getOpcode()) {
148 Opcode = MI.getOpcode();
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
|
