| /art/compiler/dex/quick/arm/ |
| arm_lir.h | 337 kThumb2StrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
338 kThumb2LdrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
343 kThumb2AddRRI12, // add rd, rn, #imm12 [11110] i [100000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
353 kThumb2SubRRI12, // sub rd, rn, #imm12 [11110] i [01010] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
366 kThumb2LdrhRRI12, // ldrh rt,[rn,#imm12] [111110001011] rt[15..12] rn[19..16] imm12[11..0].
367 kThumb2LdrshRRI12, // ldrsh rt,[rn,#imm12] [111110011011] rt[15..12] rn[19..16] imm12[11..0]
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 455 kThumb2StrRRI12, /* str(Imm,T3) rd,[rn,#imm12] [111110001100]
456 rn[19..16] rt[15..12] imm12[11..0] */
457 kThumb2LdrRRI12, /* str(Imm,T3) rd,[rn,#imm12] [111110001100]
458 rn[19..16] rt[15..12] imm12[11..0] */
467 kThumb2AddRRI12, /* add rd, rn, #imm12 [11110] i [100000] rn[19..16]
485 kThumb2SubRRI12, /* sub rd, rn, #imm12 [11110] i [01010] rn[19..16]
511 kThumb2LdrhRRI12, /* ldrh rt,[rn,#imm12] [111110001011]
512 rt[15..12] rn[19..16] imm12[11..0] */
513 kThumb2LdrshRRI12, /* ldrsh rt,[rn,#imm12] [111110011011]
514 rt[15..12] rn[19..16] imm12[11..0] *
[all...] |
| Assemble.cpp | 2644 int imm12 = insn & 0xFFF; local
[all...] |
| /art/runtime/ |
| disassembler_arm.cc | 192 uint32_t imm12 = (instruction >> 8) & 0xfff; local
194 args << '#' << ((imm12 << 4) | imm4);
675 // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii
681 uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; local
684 args << Rd << ", " << Rn << ", #" << imm12; local
688 DumpBranchTarget(args, instr_ptr + 4, (op3 == 0) ? imm12 : -imm12);
924 uint32_t imm12 = instr & 0xFFF; local
926 args << Rt << ", [" << Rn << ", #" << imm12 << "]"; local
950 uint32_t imm12 = instr & 0xFFF; local
952 args << Rt << ", [" << Rn << ", #" << imm12 << "]"; local
963 uint32_t imm12 = instr & 0xFFF; local
965 args << Rt << ", [" << Rn << ", #" << imm12 << "]"; local
995 uint32_t imm12 = instr & 0xFFF; local
997 args << Rt << ", [" << Rn << ", #" << imm12 << "]"; local
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
745 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
751 // {11-0} = imm12
752 unsigned Reg, Imm12;
758 Imm12 = 0;
780 Imm12 = Offset;
783 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
785 uint32_t Binary = Imm12 & 0xfff;
[all...] |
| ARMAddressingModes.h | 396 // addrmode2 := reg +/- imm12
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
409 assert(Imm12 < (1 << 12) && "Imm too large!");
411 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 97 int64_t Imm12 = Imm12Op.getImm();
98 assert(Imm12 >= 0 && "Invalid immediate for add/sub imm");
99 O << "#" << Imm12;
|
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 262 // {11-0} = imm12
270 int32_t Imm12 = MO1.getImm();
272 Binary = Imm12 & 0xfff;
273 if (Imm12 >= 0)
325 int32_t Imm12 = MO1.getImm();
328 if (Imm12 == INT32_MIN)
329 Imm12 = 0;
334 if (Imm12 < 0) {
335 Imm12 = -Imm12;
[all...] |
| ARMInstrInfo.td | 761 // addrmode_imm12 := reg +/- imm12
[all...] |
| ARMInstrFormats.td | 598 // {11-0} imm12/Rm
616 // {11-0} imm12/Rm
635 // {13} 1 == Rm, 0 == imm12
637 // {11-0} imm12/Rm
[all...] |
| Thumb2InstrInfo.cpp | 471 // Another common case: imm12.
|
| ARMISelDAGToDAG.cpp | 58 AM2_BASE, // Simple AM2 (+-imm12)
530 // Match simple R + imm12 operands.
610 // Leave simple R +/- imm12 operands for LDRi12
724 // Match simple R +/- imm12 operands.
[all...] |
| ARMInstrThumb2.td | 149 // t2addrmode_imm12 := reg + imm12
160 // t2ldrlabel := imm12
[all...] |
| README.txt | 505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
|
| ARMFrameLowering.cpp | 70 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | 2018 int imm12 = insn & 0xFFF; local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 153 bits<12> Imm12;
160 let Inst{21-10} = Imm12;
|
| AArch64InstrInfo.td | 565 // InOperandList, specifying imm12 and shift). Unfortunately this is not
644 (ins GPRsp:$Rn, imm_operand:$Imm12),
645 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
646 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
653 (ins GPRsp:$Rn, imm_operand:$Imm12),
654 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
655 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
664 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
665 !strconcat(cmpasmop, " $Rn, $Imm12"),
667 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 122 ARMam1_RI=1, /* reg +/- imm12 */
|
| guest_arm_toIR.c | 12449 UInt imm12 = INSN(11,0); local
12482 UInt imm12 = INSN(11,0); local
13072 UInt imm12 = (insn >> 0) & 0xFFF; \/* 11:0 *\/ local
16748 UInt imm12 = (INSN0(10,10) << 11) | (INSN1(14,12) << 8) | INSN1(7,0); local
16863 UInt imm12 = (INSN0(10,10) << 11) | (INSN1(14,12) << 8) | INSN1(7,0); local
17768 UInt imm12 = INSN1(11,0); local
18743 UInt imm12 = INSN1(11,0); local
[all...] |
| /external/qemu/ |
| arm-dis.c | 3359 unsigned int imm12 = 0; local
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intARM.c | [all...] |
| v6intARM.stdout.exp | [all...] |
| v6intThumb.c | [all...] |
