OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
full:mmu
(Results
1 - 25
of
96
) sorted by null
1
2
3
4
/external/kernel-headers/original/asm-x86/
mmu.h
8
* The x86 doesn't have a
mmu
context, but
/external/qemu/target-mips/
machine.c
62
uint16_t flags = ((env->tlb->
mmu
.r4k.tlb[i].G << 10) |
63
(env->tlb->
mmu
.r4k.tlb[i].C0 << 7) |
64
(env->tlb->
mmu
.r4k.tlb[i].C1 << 4) |
65
(env->tlb->
mmu
.r4k.tlb[i].V0 << 3) |
66
(env->tlb->
mmu
.r4k.tlb[i].V1 << 2) |
67
(env->tlb->
mmu
.r4k.tlb[i].D0 << 1) |
68
(env->tlb->
mmu
.r4k.tlb[i].D1 << 0));
71
qemu_put_betls(f, &env->tlb->
mmu
.r4k.tlb[i].VPN);
72
qemu_put_be32s(f, &env->tlb->
mmu
.r4k.tlb[i].PageMask);
73
asid = env->tlb->
mmu
.r4k.tlb[i].ASID
[
all
...]
TODO
20
Qemu's softmmu implements a x86-style
MMU
, with separate entries
23
MMU
mode.
24
MIPS has a single entry for read/write/execute and only one
MMU
mode.
27
equates to 256
MMU
modes). It also has a global flag which causes
30
each ASID change. Using the
MMU
modes to implement ASIDs hinges on
/hardware/ti/omap3/dspbridge/libbridge/inc/
mgrpriv.h
56
/* private dsp
mmu
entries */
dbdefs.h
105
/* DSP exception events (DSP/BIOS and DSP
MMU
fault) */
109
/* IVA exception events (IVA
MMU
fault) */
556
bit 1 -
MMU
Endianism (Big Endian=1, Little Endian=0)
557
bit 2 -
MMU
mixed page attribute (Mixed/ CPUES=1, TLBES =0)
558
bit 3 -
MMU
element size = 8bit (valid only for non mixed page entries)
559
bit 4 -
MMU
element size = 16bit (valid only for non mixed page entries)
560
bit 5 -
MMU
element size = 32bit (valid only for non mixed page entries)
561
bit 6 -
MMU
element size = 64bit (valid only for non mixed page entries)
578
* Element size for
MMU
mapping (8, 16, 32, or 64 bit)
/system/core/libpixelflinger/codeflinger/
armreg.h
126
#define CPU_ID_ARM740T8K 0x41807400 /* XXX no
MMU
, 8KB cache */
127
#define CPU_ID_ARM740T4K 0x41817400 /* XXX no
MMU
, 4KB cache */
134
#define CPU_ID_ARM940T 0x41029400 /* XXX no
MMU
*/
135
#define CPU_ID_ARM946ES 0x41049460 /* XXX no
MMU
*/
136
#define CPU_ID_ARM966ES 0x41049660 /* XXX no
MMU
*/
137
#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no
MMU
*/
211
#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M:
MMU
/Protection unit enable */
/external/qemu/target-arm/
cpu.h
125
uint32_t c2_base0; /*
MMU
translation table base 0. */
126
uint32_t c2_base1; /*
MMU
translation table base 1. */
127
uint32_t c2_control; /*
MMU
translation table base control. */
128
uint32_t c2_mask; /*
MMU
translation table base selection mask. */
129
uint32_t c2_base_mask; /*
MMU
translation table base 0 mask. */
132
uint32_t c3; /*
MMU
domain access control register
374
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full
MMU
. */
443
/* The ARM
MMU
allows 1k pages. */
460
/*
MMU
modes definitions */
/hardware/ti/omap3/dspbridge/inc/
dbdefs.h
105
/* DSP exception events (DSP/BIOS and DSP
MMU
fault) */
109
/* IVA exception events (IVA
MMU
fault) */
567
bit 1 -
MMU
Endianism (Big Endian=1, Little Endian=0)
568
bit 2 -
MMU
mixed page attribute (Mixed/ CPUES=1, TLBES =0)
569
bit 3 -
MMU
element size = 8bit (valid only for non mixed page entries)
570
bit 4 -
MMU
element size = 16bit (valid only for non mixed page entries)
571
bit 5 -
MMU
element size = 32bit (valid only for non mixed page entries)
572
bit 6 -
MMU
element size = 64bit (valid only for non mixed page entries)
589
* Element size for
MMU
mapping (8, 16, 32, or 64 bit)
mgrpriv.h
56
/* private dsp
mmu
entries */
/prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/config/
linux.h
2
MMU
, using ELF at the compiler level but possibly FLT for final
3
linked executables and shared libraries in some no-
MMU
cases, and
/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/config/
linux.h
2
MMU
, using ELF at the compiler level but possibly FLT for final
3
linked executables and shared libraries in some no-
MMU
cases, and
/external/elfutils/backends/
ppc_auxv.c
46
"4xxmac\0" "
mmu
\0" "fpu\0" "altivec\0"
/external/qemu/docs/
CPU-EMULATION.TXT
21
(described below in "
MMU
emulation"), there are actually two TB caches per
40
MMU
Emulation:
68
When initializing the
MMU
emulation, one can define several zones of the
/external/kernel-headers/original/linux/
backing-dev.h
41
* - These flags let !
MMU
mmap() govern direct device mapping vs immediate
/prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/
desc_32.h
24
#include <asm/
mmu
.h>
/prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/
desc_32.h
24
#include <asm/
mmu
.h>
/prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/
desc_32.h
24
#include <asm/
mmu
.h>
/prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/
desc_32.h
24
#include <asm/
mmu
.h>
/prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/
desc_32.h
24
#include <asm/
mmu
.h>
/external/qemu/
cpu-defs.h
108
/* The meaning of the
MMU
modes is defined in the target code. */ \
153
/* soft
mmu
support */ \
/external/grub/netboot/
smc9000.c
85
/* Reset the
MMU
*/
89
/* Note: It doesn't seem that waiting for the
MMU
busy is needed here,
91
* of issuing another
MMU
command right after this */
197
/* convert to
MMU
pages */
228
printf("SMC9000: Memory allocation timed out, resetting
MMU
.\n");
/external/kernel-headers/original/asm-arm/
system.h
20
#define CR_M (1 << 0) /*
MMU
enable */
28
#define CR_S (1 << 8) /* System
MMU
protection */
29
#define CR_R (1 << 9) /* ROM
MMU
protection */
/bionic/libc/kernel/arch-x86/asm/
desc_32.h
29
#include <asm/
mmu
.h>
/development/ndk/platforms/android-9/arch-x86/include/asm/
desc_32.h
29
#include <asm/
mmu
.h>
/external/dhcpcd/
platform-linux.c
57
"
MMU
"
Completed in 5175 milliseconds
1
2
3
4