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  /external/llvm/test/CodeGen/X86/
2010-05-12-FastAllocKills.ll 9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
18 ; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
22 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
23 ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4
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  /external/llvm/test/CodeGen/ARM/
eh-dispcont.ll 47 ; ARM-PIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
48 ; ARM-PIC: add pc, [[REG0]], [[REG1]]
58 ; ARM-NOPIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
59 ; ARM-NOPIC: mov pc, [[REG0]]
69 ; THUMB1-PIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
70 ; THUMB1-PIC: ldr [[REG0]]
71 ; THUMB1-PIC: adds [[REG0]], [[REG0]], [[REG1]]
72 ; THUMB1-PIC: mov pc, [[REG0]]
    [all...]
fast-isel-pic.ll 12 ; THUMB: movw [[reg0:r[0-9]+]],
13 ; THUMB: movt [[reg0]],
14 ; THUMB: add [[reg0]], pc
16 ; THUMB-ELF: ldr r[[reg0:[0-9]+]],
18 ; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
2011-11-29-128bitArithmetics.ll 32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
63 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
94 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
125 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
156 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}
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  /dalvik/vm/compiler/codegen/mips/Mips32/
Gen.cpp 250 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; local
252 newLIR4(cUnit, kMipsExt, reg0, reg0, 0, 31-1 /* size-1 */);
254 newLIR2(cUnit, kMipsSll, reg0, 1);
255 newLIR2(cUnit, kMipsSrl, reg0, 1);
257 storeWordDisp(cUnit, rSELF, offset, reg0);
259 dvmCompilerClobber(cUnit, reg0);
289 int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg; local
293 newLIR3(cUnit, kMipsSlt, tReg, reg0, reg1);
296 newLIR3(cUnit, kMipsSlt, tReg, reg1, reg0);
    [all...]
  /dalvik/vm/compiler/codegen/arm/Thumb/
Gen.cpp 219 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; local
222 newLIR2(cUnit, kThumbAndRR, reg0, signMask);
224 storeWordDisp(cUnit, r6SELF, offset, reg0);
226 dvmCompilerClobber(cUnit, reg0);
254 int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg; local
256 newLIR2(cUnit, kThumbCmpRR, reg0, reg1);
259 newLIR2(cUnit, kThumbMovRR, reg0, reg1);
262 newLIR3(cUnit, kThumbStrRRI5, reg0, r6SELF, offset >> 2);
265 dvmCompilerClobber(cUnit,reg0);
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_fragshader.c 48 GLuint reg0 = 0; local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos);
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos);
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos);
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos);
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos);
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos);
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos);
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos);
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos)
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 48 GLuint reg0 = 0; local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos);
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos);
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos);
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos);
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos);
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos);
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos);
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos);
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos)
    [all...]
  /external/llvm/test/CodeGen/Thumb2/
2010-06-14-NEONCoalescer.ll 8 ; 140 %reg1038:dsub_0<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
9 ; 148 %reg1038:dsub_1<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
  /external/pixman/pixman/
pixman-arm-simd-asm.h 99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable
102 op&r&cond WK&reg0, [base], #4
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3} variable
111 op&r&cond WK&reg0, [base], #4
114 op&m&cond&ia base!, {WK&reg0,WK&reg1} variable
117 op&r&cond WK&reg0, [base], #4
119 op&r&cond&h WK&reg0, [base], #2
121 op&r&cond&b WK&reg0, [base], #1
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3 variable
131 stm&cond&db base, {WK&reg0,WK&reg1} variable
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  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 248 unsigned Reg0 = Op0.getReg();
249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
253 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
255 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
  /hardware/ti/omap3/dspbridge/inc/
dbg_zones.h 35 * - opt1 and opt2 are user defined zones e.g. "Reg0 Write" *
  /hardware/ti/omap3/dspbridge/libbridge/inc/
dbg_zones.h 35 * - opt1 and opt2 are user defined zones e.g. "Reg0 Write" *
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]
ARMAsmPrinter.cpp 470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
471 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
    [all...]
Thumb2SizeReduction.cpp 643 unsigned Reg0 = MI->getOperand(0).getReg();
649 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
652 if (Reg0 != Reg2) {
655 if (Reg1 != Reg0)
662 } else if (Reg0 != Reg1) {
666 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
672 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
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  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 524 uint16_t Reg0;
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
530 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
536 return Reg0;
541 return Reg0;
547 Reg0 = Reg1;
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
145 if (HasDef && Reg0 == Reg1 &&
148 Reg0 = Reg2;
150 } else if (HasDef && Reg0 == Reg2 &&
153 Reg0 = Reg1;
164 MI->getOperand(0).setReg(Reg0);
AggressiveAntiDepBreaker.cpp 423 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
425 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
426 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
427 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
802 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
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CriticalAntiDepBreaker.cpp 153 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
155 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
156 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
157 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
523 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
  /external/llvm/lib/Target/AArch64/InstPrinter/
AArch64InstPrinter.cpp 328 unsigned Reg0 = MI->getOperand(0).getReg();
331 if (isStackReg(Reg0) || isStackReg(Reg1)) {
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp     [all...]
  /external/chromium_org/v8/src/mips/
macro-assembler-mips.cc 418 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) {
424 xor_(reg0, reg0, scratch);
430 nor(scratch, reg0, zero_reg);
431 sll(at, reg0, 15);
432 addu(reg0, scratch, at);
435 srl(at, reg0, 12);
436 xor_(reg0, reg0, at);
439 sll(at, reg0, 2)
    [all...]
  /external/v8/src/mips/
macro-assembler-mips.cc 418 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) {
424 xor_(reg0, reg0, scratch);
430 nor(scratch, reg0, zero_reg);
431 sll(at, reg0, 15);
432 addu(reg0, scratch, at);
435 srl(at, reg0, 12);
436 xor_(reg0, reg0, at);
439 sll(at, reg0, 2)
    [all...]
  /external/skia/gm/
bitmaprect.cpp 245 static skiagm::GMRegistry reg0(MyFactory0);

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