| /external/llvm/test/CodeGen/ARM/ |
| fnmacs.ll | 8 ; VFP2: vmls.f32
11 ; NEON: vmls.f32
24 ; VFP2: vmls.f64
27 ; NEON: vmls.f64
|
| vmls.ll | 5 ;CHECK: vmls.i8
16 ;CHECK: vmls.i16
27 ;CHECK: vmls.i32
38 ;CHECK: vmls.f32
49 ;CHECK: vmls.i8
60 ;CHECK: vmls.i16
71 ;CHECK: vmls.i32
82 ;CHECK: vmls.f32
|
| fmacs.ll | 55 ; It's possible to make use of fp vmla / vmls on Cortex-A9.
|
| /external/llvm/test/MC/ARM/ |
| neon-mul-accum-encoding.s | 54 vmls.i8 d16, d18, d17
55 vmls.i16 d16, d18, d17
56 vmls.i32 d16, d18, d17
57 vmls.f32 d16, d18, d17
58 vmls.i8 q9, q8, q10
59 vmls.i16 q9, q8, q10
60 vmls.i32 q9, q8, q10
61 vmls.f32 q9, q8, q10
62 vmls.i16 q4, q12, d6[2]
64 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3
[all...] |
| neont2-mul-accum-encoding.s | 58 vmls.i8 d16, d18, d17
59 vmls.i16 d16, d18, d17
60 vmls.i32 d16, d18, d17
61 vmls.f32 d16, d18, d17
62 vmls.i8 q9, q8, q10
63 vmls.i16 q9, q8, q10
64 vmls.i32 q9, q8, q10
65 vmls.f32 q9, q8, q10
66 vmls.i16 q4, q12, d6[2]
68 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09
[all...] |
| simple-fp-encoding.s | 102 vmls.f64 d16, d18, d17
103 vmls.f32 s1, s2, s0
105 @ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
106 @ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.S | 30 VMLS.I16 d0,d16,d30
35 VMLS.I16 d2,d16,d30
40 VMLS.I16 d4,d16,d30
45 VMLS.I16 d6,d16,d30
|
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.S | 63 VMLS.I16 d28,d12,d30
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.S | 151 VMLS.I32 q3,q0,q14
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 112 ; VMLS dRes0, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
129 ; VMLS dRes1, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
146 ; VMLS dRes2, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
163 ; VMLS dRes3, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
180 ; VMLS dRes4, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
197 ; VMLS dRes5, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
214 ; VMLS dRes6, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
231 ; VMLS dRes7, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
247 ; VMLS dRes8, dSrcB, dCoeff5 ;// Acc -= 5*(b+e)
261 ; VMLS qAcc01, qSumBE, qCoeff5 ;// Acc -= 20*(b+e)
[all...] |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 90 VMLS dRes0, dSumBE0, dCoeff5 ;// Acc -= 20*(b+e)
98 VMLS dRes1, dSumBE0, dCoeff5 ;// Acc -= 20*(b+e)
106 VMLS dRes2, dSumBE0, dCoeff5 ;// Acc -= 20*(b+e)
114 VMLS dRes3, dSumBE0, dCoeff5 ;// Acc -= 20*(b+e)
|
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 104 ; VMLS dRes0, dTemp2, dCoeff5 ;// Acc -= 5*(b+e)
123 ; VMLS dRes2, dTemp2, dCoeff5 ;// Acc -= 5*(b+e)
141 ; VMLS dRes4, dTemp2, dCoeff5 ;// Acc -= 5*(b+e)
157 VMLS dRes6, dTemp2, dCoeff5 ;// Acc -= 5*(b+e)
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 41 // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
42 // a VMLA / VMLS will cause 4 cycle stall.
|
| /external/valgrind/main/none/tests/arm/ |
| vfp.stdout.exp | 215 ---- VMLS (fp) ----
216 vmls.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
217 vmls.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
218 vmls.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
219 vmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
220 vmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
221 vmls.f64 d20, d25, d22 :: Qd 0x409067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
222 vmls.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
223 vmls.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
224 vmls.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 0000000
[all...] |
| vfp.c | [all...] |
| neon128.c | [all...] |
| neon64.c | [all...] |
| neon64.stdout.exp | [all...] |
| /hardware/samsung_slsi/exynos5/libswconverter/ |
| csc_ARGB8888_to_YUV420SP_NEON.s | 84 vmls.u16 q8,q4,q11 @q0:U -(38 * R[k]) @128<<6+ 32 + u>>2
85 vmls.u16 q8,q5,q12 @-(74 * G[k])
90 vmls.u16 q7,q5,q14 @q0:U -(94 * G[k]) @128<<6+ 32 + v>>2
91 vmls.u16 q7,q6,q15 @-(18 * B[k])
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| fp-encoding.txt | 94 # CHECK: vmls.f64 d16, d18, d17
97 # CHECK: vmls.f32 s1, s2, s0
|
| neont2.txt | 622 # CHECK: vmls.i8 d16, d18, d17
624 # CHECK: vmls.i16 d16, d18, d17
626 # CHECK: vmls.i32 d16, d18, d17
628 # CHECK: vmls.f32 d16, d18, d17
630 # CHECK: vmls.i8 q9, q8, q10
632 # CHECK: vmls.i16 q9, q8, q10
634 # CHECK: vmls.i32 q9, q8, q10
636 # CHECK: vmls.f32 q9, q8, q10
[all...] |
| neon.txt | 725 # CHECK: vmls.i8 d16, d18, d17
727 # CHECK: vmls.i16 d16, d18, d17
729 # CHECK: vmls.i32 d16, d18, d17
731 # CHECK: vmls.f32 d16, d18, d17
733 # CHECK: vmls.i8 q9, q8, q10
735 # CHECK: vmls.i16 q9, q8, q10
737 # CHECK: vmls.i32 q9, q8, q10
739 # CHECK: vmls.f32 q9, q8, q10
[all...] |
| /external/clang/include/clang/Basic/ |
| arm_neon.td | 175 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
479 def MLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>;
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm.cc | 578 COMPARE(vmls(d2, d1, d0),
579 "ee012b40 vmls.f64 d2, d1, d0");
580 COMPARE(vmls(d6, d4, d5, cc),
[all...] |
| /external/clang/test/CodeGen/ |
| arm_neon_intrinsics.c | [all...] |
