Lines Matching refs:em64t
31 // need to use EM64T-specifics - new registers, defines from enc_prvt, etc...
93 instruction to handle additional registers on EM64T:
99 the second line is for EM64T only
109 {OpcodeInfo::em64t, {REX_W, 0xFF, _1}, {r_m64}, DU },
331 // TheManual says it's not always supported in em64t mode, thus excluding it
357 {OpcodeInfo::em64t, {REX_W, 0x81, opc_ext, id}, {r_m64, imm32s}, def_use },\
361 {OpcodeInfo::em64t, {REX_W, 0x83, opc_ext, ib}, {r_m64, imm8s}, def_use },\
367 {OpcodeInfo::em64t, {REX_W, opcode_starts_from+1, _r}, {r_m64, r64}, def_use },\
373 {OpcodeInfo::em64t, {REX_W, opcode_starts_from+3, _r}, {r64, r_m64}, def_use },
430 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xB1, _r}, {r_m64, r64, RAX}, DU_DU_DU },
475 {OpcodeInfo::em64t, {0xFF, _2}, {r_m64}, U },
490 {OpcodeInfo::em64t, {REX_W, 0x99}, {RDX, RAX}, D_U },
499 {OpcodeInfo::em64t, {REX_W, 0x0F, 0x40 + ConditionMnemonic_##cc, _r}, {r64, r_m64}, DU_U }, \
537 {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2D, _r}, {r64, xmm_m64}, D_U },
545 {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2C, _r}, {r64, xmm_m64}, D_U },
560 {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2D, _r}, {r64, xmm_m32}, D_U},
568 {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2C, _r}, {r64, xmm_m32}, D_U},
576 {OpcodeInfo::em64t, {REX_W, 0xF2, 0x0F, 0x2A, _r}, {xmm64, r_m64}, D_U},
584 {OpcodeInfo::em64t, {REX_W, 0xF3, 0x0F, 0x2A, _r}, {xmm32, r_m64}, D_U},
598 {OpcodeInfo::em64t, {REX_W, 0xFF, _1}, {r_m64}, DU },
998 {OpcodeInfo::em64t, {REX_W, 0xF7, _7}, {RDX, RAX, r_m64}, DU_DU_U },
1013 // {OpcodeInfo::em64t, {REX_W, 0xF7, _5}, {RDX, RAX, r_m64}, D_DU_U },
1017 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xAF, _r}, {r64,r_m64}, DU_U },
1020 {OpcodeInfo::em64t, {REX_W, 0x6B, _r, ib}, {r64,r_m64,imm8s}, D_DU_U },
1023 {OpcodeInfo::em64t, {REX_W, 0x6B, _r, ib}, {r64,imm8s}, DU_U },
1026 {OpcodeInfo::em64t, {REX_W, 0x69, _r, id}, {r64,r_m64,imm32s}, D_U_U },
1037 {OpcodeInfo::em64t, {REX_W, 0xF7, _4}, {RDX, RAX, r_m64}, D_DU_U },
1046 {OpcodeInfo::em64t, {REX_W, 0xFF, _0}, {r_m64}, DU },
1095 {OpcodeInfo::em64t, {0xFF, _4}, {r_m64}, U },
1111 {OpcodeInfo::em64t, {0x8D, _r}, {r64, m}, D_U },
1115 {OpcodeInfo::em64t, {REX_W, 0x8D, _r}, {r64, m8}, D_U },
1117 {OpcodeInfo::em64t, {REX_W, 0x8D, _r}, {r64, m16}, D_U },
1119 {OpcodeInfo::em64t, {REX_W, 0x8D, _r}, {r64, m32}, D_U },
1121 {OpcodeInfo::em64t, {REX_W, 0x8D, _r}, {r64, m64}, D_U },
1149 {OpcodeInfo::em64t, {REX_W, 0x89, _r}, {r_m64,r64}, D_U },
1154 {OpcodeInfo::em64t, {REX_W, 0x8B, _r}, {r64,r_m64}, D_U },
1160 {OpcodeInfo::em64t, {REX_W, 0xB8|rd}, {r64,imm64}, D_U },
1165 {OpcodeInfo::em64t, {REX_W, 0xC7, _0}, {r_m64,imm32s}, D_U },
1196 // {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x6E, _r}, {xmm64, r_m64}, D_U },
1197 // {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x7E, _r}, {r_m64, xmm64}, D_U },
1198 {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x6E, _r}, {xmm64, r64}, D_U },
1199 {OpcodeInfo::em64t, {REX_W, 0x66, 0x0F, 0x7E, _r}, {r64, xmm64}, D_U },
1321 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xBE, _r}, {r64, r_m8s}, D_U },
1324 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xBF, _r}, {r64, r_m16s}, D_U },
1326 {OpcodeInfo::em64t, {REX_W, 0x63, _r}, {r64, r_m32s}, D_U },
1334 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xB6, _r}, {r64, r_m8u}, D_U },
1337 {OpcodeInfo::em64t, {REX_W, 0x0F, 0xB7, _r}, {r64, r_m16u}, D_U },
1340 {OpcodeInfo::em64t, {0x8B, _r}, {r64, r_m32u}, D_U },
1362 {OpcodeInfo::em64t, {REX_W, 0xF7, _3}, {r_m64}, DU },
1377 {OpcodeInfo::em64t, {REX_W, 0xF7, _2}, {r_m64}, DU },
1385 {OpcodeInfo::em64t, {0x8F, _0}, {r_m64}, D },
1389 {OpcodeInfo::em64t, {0x58|rd }, {r64}, D },
1409 {OpcodeInfo::em64t, {0xFF, _6}, {r_m64}, U },
1413 {OpcodeInfo::em64t, {0x50|rd }, {r64}, U },
1418 // {OpcodeInfo::em64t, {0x68}, {imm64}, U },
1480 {OpcodeInfo::em64t, {REX_W, 0xD3, slash_num}, {r_m64, CL}, DU_U },\
1483 {OpcodeInfo::em64t, {REX_W, 0xC1, slash_num, ib}, {r_m64, imm8}, DU_U },\
1538 {OpcodeInfo::em64t, {REX_W, 0xF7, _0, id}, {r_m64,imm32s}, U_U },
1544 {OpcodeInfo::em64t, {REX_W, 0x85, _r}, {r_m64,r64}, U_U },
1643 {OpcodeInfo::em64t, {REX_W, 0xAB}, {RDI, RCX, RAX}, DU_DU_U },
1659 {OpcodeInfo::em64t, {0xA4}, {r64,r64,RCX}, DU_DU_DU },
1666 {OpcodeInfo::em64t, {Size16, 0xA5}, {r64,r64,RCX}, DU_DU_DU },
1673 {OpcodeInfo::em64t, {0xA5}, {r64,r64,RCX}, DU_DU_DU },
1679 {OpcodeInfo::em64t, {REX_W,0xA5}, {r64,r64,RCX}, DU_DU_DU },
1686 {OpcodeInfo::em64t, {0xA6}, {RSI,RDI,RCX}, DU_DU_DU },
1693 {OpcodeInfo::em64t, {Size16, 0xA7}, {RSI,RDI,RCX}, DU_DU_DU },
1700 {OpcodeInfo::em64t, {0xA7}, {RSI,RDI,RCX}, DU_DU_DU },
1811 if (oinfo.platf == OpcodeInfo::em64t) { continue; }
