Lines Matching refs:base_addr
331 inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
333 outw(internal_addr, base_addr + TLAN_DIO_ADR);
334 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
338 inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
340 outw(internal_addr, base_addr + TLAN_DIO_ADR);
341 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
345 inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
347 outw(internal_addr, base_addr + TLAN_DIO_ADR);
348 return (inl(base_addr + TLAN_DIO_DATA));
352 inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
354 outw(internal_addr, base_addr + TLAN_DIO_ADR);
355 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
359 inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
361 outw(internal_addr, base_addr + TLAN_DIO_ADR);
362 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
366 inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
368 outw(internal_addr, base_addr + TLAN_DIO_ADR);
369 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
706 TLan_MiiSync( dev->base_addr );
709 TLan_MiiSync( dev->base_addr );
727 TLan_MiiSync( dev->base_addr );
730 TLan_MiiSync(dev->base_addr);
748 TLan_MiiSync( dev->base_addr );
819 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
891 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
1013 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
1014 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
1019 TLan_MiiSync(dev->base_addr);
1025 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Start ( 01b ) */
1026 TLan_MiiSendData( dev->base_addr, 0x2, 2 ); /* Read ( 10b ) */
1027 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1028 TLan_MiiSendData( dev->base_addr, reg, 5 ); /* Register # */
1169 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
1170 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
1175 TLan_MiiSync( dev->base_addr );
1181 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Start ( 01b ) */
1182 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Write ( 01b ) */
1183 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */
1184 TLan_MiiSendData( dev->base_addr, reg, 5 ); /* Register # */
1186 TLan_MiiSendData( dev->base_addr, 0x2, 2 ); /* Send ACK */
1187 TLan_MiiSendData( dev->base_addr, val, 16 ); /* Send Data */
1899 release_region( dev->base_addr, 0x10 );
2022 dev->base_addr = pci_io_base;
2040 dev->base_addr = ioaddr;
2094 (int) dev->base_addr,
2113 release_region( dev->base_addr, 0x10);
2258 if (!request_region( dev->base_addr, 0x10, TLanSignature )) {
2261 dev->base_addr,
2277 release_region( dev->base_addr, 0x10 );
2338 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION );
2508 outl( virt_to_bus( tail_list ), dev->base_addr + TLAN_CH_PARM );
2509 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD );
2565 host_int = inw( dev->base_addr + TLAN_HOST_INT );
2566 outw( host_int, dev->base_addr + TLAN_HOST_INT );
2574 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD );
2604 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
2644 TLan_PrintDio( dev->base_addr );
2688 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
2689 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF );
2691 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
2692 TLan_DioWrite8( dev->base_addr
2696 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, 0xFFFFFFFF );
2697 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, 0xFFFFFFFF );
2713 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, hash1 );
2714 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, hash2 );
2814 outl( virt_to_bus( head_list ), dev->base_addr + TLAN_CH_PARM );
2822 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
2976 outl( virt_to_bus( head_list ), dev->base_addr + TLAN_CH_PARM );
2982 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
3057 outl( virt_to_bus( head_list ), dev->base_addr + TLAN_CH_PARM );
3101 error = inl( dev->base_addr + TLAN_CH_PARM );
3104 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
3115 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS );
3117 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts );
3170 outl( virt_to_bus( head_list ), dev->base_addr + TLAN_CH_PARM );
3255 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
3467 outw( TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR );
3468 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3469 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3470 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
3471 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
3473 outw( TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR );
3474 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3475 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3476 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
3477 rx_over = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
3479 outw( TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR );
3480 def_tx = inb( dev->base_addr + TLAN_DIO_DATA );
3481 def_tx += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3482 crc = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
3483 code = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
3485 outw( TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
3486 multi_col = inb( dev->base_addr + TLAN_DIO_DATA );
3487 multi_col += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3488 single_col = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
3489 single_col += inb( dev->base_addr + TLAN_DIO_DATA + 3 ) << 8;
3491 outw( TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
3492 excess_col = inb( dev->base_addr + TLAN_DIO_DATA );
3493 late_col = inb( dev->base_addr + TLAN_DIO_DATA + 1 );
3494 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
3543 data = inl(dev->base_addr + TLAN_HOST_CMD);
3545 outl(data, dev->base_addr + TLAN_HOST_CMD);
3551 data = inl(dev->base_addr + TLAN_HOST_CMD);
3553 outl(data, dev->base_addr + TLAN_HOST_CMD);
3558 TLan_DioWrite32( dev->base_addr, (u16) i, 0 );
3564 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
3568 outl( TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD );
3569 outl( TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD );
3573 outw( TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR );
3574 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
3581 TLan_DioWrite8( dev->base_addr, TLAN_INT_DIS, data8 );
3589 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x0a );
3591 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x00 );
3594 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x08 );
3601 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
3631 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, data );
3636 TLan_DioWrite8( dev->base_addr, TLAN_NET_MASK, data );
3637 TLan_DioWrite16( dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7 );
3670 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
3679 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
3687 sio = TLan_DioRead8( dev->base_addr, TLAN_NET_SIO );
3689 TLan_DioWrite8( dev->base_addr, TLAN_NET_SIO, sio );
3695 outb( ( TLAN_HC_INT_ON >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
3697 outb( ( TLAN_HC_REQ_INT >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
3699 outl( virt_to_bus( priv->rxList ), dev->base_addr + TLAN_CH_PARM );
3700 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD );
3738 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, mac[i] );
3741 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, 0 );
