Lines Matching refs:BrCond
102 /// BrCond - Conditions for end of block conditional branches.
120 SmallVector<MachineOperand, 4> BrCond;
439 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
441 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
501 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
636 BBI.BrCond.clear();
638 !TII->AnalyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
641 if (BBI.BrCond.size()) {
728 if (BBI.BrCond.size()) {
734 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
764 if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
793 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
810 FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
828 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
843 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
851 FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
1030 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1111 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1177 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
1178 CvtBBI->BrCond.end());
1255 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1258 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;