Lines Matching refs:N0
255 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
256 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
579 SDValue N0, N1, N2;
580 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
586 SDValue N0, SDValue N1) {
587 EVT VT = N0.getValueType();
588 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
593 cast<ConstantSDNode>(N0.getOperand(1)),
595 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
597 if (N0.hasOneUse()) {
599 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
600 N0.getOperand(0), N1);
602 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
607 if (isa<ConstantSDNode>(N0)) {
612 cast<ConstantSDNode>(N0));
617 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
618 N1.getOperand(0), N0);
830 SDValue N0 = Op.getOperand(0);
831 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
838 if (N0 == N1)
851 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
888 SDValue N0 = Op.getOperand(0);
890 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
892 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
894 N0 = PromoteOperand(N0, PVT, Replace);
895 if (N0.getNode() == 0)
898 AddToWorkList(N0.getNode());
900 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
906 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1235 SDValue N0 = N->getOperand(0);
1239 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1240 SDValue Ops[] = { N1, N0 };
1362 SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1364 EVT VT = N0.getValueType();
1365 SDValue N00 = N0.getOperand(0);
1366 SDValue N01 = N0.getOperand(1);
1372 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1377 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1384 SDValue N0 = N->getOperand(0);
1386 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1388 EVT VT = N0.getValueType();
1397 return N0;
1398 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1403 if (N0.getOpcode() == ISD::UNDEF)
1404 return N0;
1412 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1415 return N0;
1417 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1424 if (N1C && N0.getOpcode() == ISD::SUB)
1425 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1429 N0.getOperand(1));
1431 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1435 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1436 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1437 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1441 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1443 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1446 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1447 return N0.getOperand(0);
1450 N0 == N1.getOperand(1).getOperand(0))
1455 N0 == N1.getOperand(1).getOperand(1))
1461 N0 == N1.getOperand(0).getOperand(1))
1466 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1467 SDValue N00 = N0.getOperand(0);
1468 SDValue N01 = N0.getOperand(1);
1474 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1485 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1493 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1498 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1499 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1503 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1513 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1517 if (N0.getOpcode() == ISD::SHL &&
1518 N0.getOperand(0).getOpcode() == ISD::SUB)
1520 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1524 N0.getOperand(0).getOperand(1),
1525 N0.getOperand(1)));
1542 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1543 N0.getOperand(0).getValueType() == MVT::i1 &&
1546 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1554 SDValue N0 = N->getOperand(0);
1556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1558 EVT VT = N0.getValueType();
1562 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1568 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1572 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1578 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1586 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1595 SDValue N0 = N->getOperand(0);
1598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1604 N1, N0, CarryIn);
1608 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1637 SDValue N0 = N->getOperand(0);
1639 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1643 EVT VT = N0.getValueType();
1652 return N0;
1657 if (N0 == N1)
1664 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1668 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1670 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1673 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1674 return N0.getOperand(1);
1676 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1677 return N0.getOperand(0);
1686 if (N0.getOpcode() == ISD::ADD &&
1687 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1688 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1689 N0.getOperand(1).getOperand(0) == N1)
1690 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1691 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1693 if (N0.getOpcode() == ISD::ADD &&
1694 N0.getOperand(1).getOpcode() == ISD::ADD &&
1695 N0.getOperand(1).getOperand(1) == N1)
1697 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1699 if (N0.getOpcode() == ISD::SUB &&
1700 N0.getOperand(1).getOpcode() == ISD::SUB &&
1701 N0.getOperand(1).getOperand(1) == N1)
1703 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1706 if (N0.getOpcode() == ISD::UNDEF)
1707 return N0;
1712 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1730 SDValue N0 = N->getOperand(0);
1732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1734 EVT VT = N0.getValueType();
1738 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1743 if (N0 == N1)
1750 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1755 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1763 SDValue N0 = N->getOperand(0);
1769 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1791 SDValue N0 = N->getOperand(0);
1793 EVT VT = N0.getValueType();
1796 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1807 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1810 N0IsConst = dyn_cast<ConstantSDNode>(N0) != 0;
1811 ConstValue0 = N0IsConst? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue() : APInt();
1818 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1822 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1828 return N0;
1832 DAG.getConstant(0, VT), N0);
1835 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1837 getShiftAmountTy(N0.getValueType())));
1845 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1847 getShiftAmountTy(N0.getValueType()))));
1852 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1853 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1854 isa<ConstantSDNode>(N0.getOperand(1)))) {
1856 N1, N0.getOperand(1));
1859 N0.getOperand(0), C3);
1867 if (N0.getOpcode() == ISD::SHL &&
1868 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1869 isa<ConstantSDNode>(N0.getOperand(1))) &&
1870 N0.getNode()->hasOneUse()) {
1871 Sh = N0; Y = N1;
1875 Sh = N1; Y = N0;
1887 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1888 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1889 isa<ConstantSDNode>(N0.getOperand(1))))
1891 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
1892 N0.getOperand(0), N1),
1894 N0.getOperand(1), N1));
1897 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
1905 SDValue N0 = N->getOperand(0);
1907 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1922 return N0;
1926 DAG.getConstant(0, VT), N0);
1930 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1932 N0, N1);
1946 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
1948 getShiftAmountTy(N0.getValueType())));
1951 // Add (N0 < 0) ? abs2 - 1 : 0;
1955 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
1979 if (N0.getOpcode() == ISD::UNDEF)
1989 SDValue N0 = N->getOperand(0);
1991 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
2006 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2008 getShiftAmountTy(N0.getValueType())));
2020 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2031 if (N0.getOpcode() == ISD::UNDEF)
2041 SDValue N0 = N->getOperand(0);
2043 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2053 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2054 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2060 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2066 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2073 if (N0.getOpcode() == ISD::UNDEF)
2083 SDValue N0 = N->getOperand(0);
2085 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2094 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2105 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2113 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2119 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2126 if (N0.getOpcode() == ISD::UNDEF)
2136 SDValue N0 = N->getOperand(0);
2147 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2148 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2149 getShiftAmountTy(N0.getValueType())));
2151 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2161 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2163 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2174 SDValue N0 = N->getOperand(0);
2185 return DAG.getConstant(0, N0.getValueType());
2187 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2197 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2199 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2286 // Compute the low part as N0.
2316 // Compute the low part as N0.
2362 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2363 EVT VT = N0.getValueType();
2364 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2367 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2377 EVT Op0VT = N0.getOperand(0).getValueType();
2378 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2379 N0.getOpcode() == ISD::SIGN_EXTEND ||
2381 (N0.getOpcode() == ISD::ANY_EXTEND &&
2383 (N0.getOpcode() == ISD::TRUNCATE &&
2390 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2391 N0.getOperand(0).getValueType(),
2392 N0.getOperand(0), N1.getOperand(0));
2394 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2401 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2402 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2403 N0.getOperand(1) == N1.getOperand(1)) {
2404 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2405 N0.getOperand(0).getValueType(),
2406 N0.getOperand(0), N1.getOperand(0));
2408 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2409 ORNode, N0.getOperand(1));
2419 if ((N0.getOpcode() == ISD::BITCAST ||
2420 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2422 SDValue In0 = N0.getOperand(0);
2431 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2444 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2445 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2447 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2450 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2469 N0.getOperand(0), N1.getOperand(0));
2480 SDValue N0 = N->getOperand(0);
2483 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2494 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2495 return N0;
2500 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2503 return N0;
2507 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2514 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2517 return N0;
2523 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2527 if (N1C && N0.getOpcode() == ISD::OR)
2528 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2532 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2533 SDValue N0Op0 = N0.getOperand(0);
2538 N0.getValueType(), N0Op0);
2546 CombineTo(N0.getNode(), Zext);
2556 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2557 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2558 N0.getOpcode() == ISD::LOAD) {
2559 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2560 N0 : N0.getOperand(0) );
2644 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2650 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2658 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2665 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2672 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2690 getSetCCResultType(N0.getSimpleValueType())))))
2691 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2697 if (N0.getOpcode() == N1.getOpcode()) {
2709 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2710 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2719 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2725 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2730 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2731 N0.hasOneUse()) {
2732 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2741 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2748 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2756 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2757 (N0.getOpcode() == ISD::ANY_EXTEND &&
2758 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2759 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2761 ? cast<LoadSDNode>(N0.getOperand(0))
2762 : cast<LoadSDNode>(N0);
2764 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2824 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2826 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2836 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2840 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2841 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2842 CombineTo(N0.getNode(), NewAdd);
2856 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2870 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2871 std::swap(N0, N1);
2873 std::swap(N0, N1);
2874 if (N0.getOpcode() == ISD::AND) {
2875 if (!N0.getNode()->hasOneUse())
2877 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2880 N0 = N0.getOperand(0);
2894 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2895 std::swap(N0, N1);
2896 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2898 if (!N0.getNode()->hasOneUse() ||
2902 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2910 SDValue N00 = N0->getOperand(0);
2976 SDValue N0 = N.getOperand(0);
2981 if (N0.getOpcode() != ISD::SRL)
2983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2989 if (N0.getOpcode() != ISD::SHL)
2991 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3016 Parts[Num] = N0.getOperand(0).getNode();
3023 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3037 if (N0.getOpcode() != ISD::OR)
3039 SDValue N00 = N0.getOperand(0);
3040 SDValue N01 = N0.getOperand(1);
3094 SDValue N0 = N->getOperand(0);
3097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3107 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3110 return N0;
3113 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3114 return N0;
3121 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3130 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3133 return N0;
3138 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3142 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3145 BSwap = MatchBSwapHWordLow(N, N0, N1);
3150 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3155 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3156 isa<ConstantSDNode>(N0.getOperand(1))) {
3157 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3160 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3161 N0.getOperand(0), N1),
3165 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3202 getSetCCResultType(N0.getValueType())))))
3203 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3209 if (N0.getOpcode() == N1.getOpcode()) {
3215 if (N0.getOpcode() == ISD::AND &&
3217 N0.getOperand(1).getOpcode() == ISD::Constant &&
3220 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3224 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3228 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3230 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3231 N0.getOperand(0), N1.getOperand(0));
3238 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3410 SDValue N0 = N->getOperand(0);
3413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3415 EVT VT = N0.getValueType();
3423 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3426 return N0;
3430 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3433 if (N0.getOpcode() == ISD::UNDEF)
3434 return N0;
3442 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3445 return N0;
3447 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3452 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3459 switch (N0.getOpcode()) {
3465 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3466 N0.getOperand(3), NotCC);
3472 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3473 N0.getNode()->hasOneUse() &&
3474 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3475 SDValue V = N0.getOperand(0);
3476 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3484 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3485 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3487 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3496 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3497 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3499 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3507 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3508 N0->getOperand(1) == N1) {
3509 SDValue X = N0->getOperand(0);
3515 if (N1C && N0.getOpcode() == ISD::XOR) {
3516 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3517 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3519 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3523 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3528 if (N0 == N1)
3532 if (N0.getOpcode() == N1.getOpcode()) {
3616 SDValue N0 = N->getOperand(0);
3618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3620 EVT VT = N0.getValueType();
3628 return N0;
3634 return N0;
3636 if (N0.getOpcode() == ISD::UNDEF)
3652 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
3665 if (N1C && N0.getOpcode() == ISD::SHL &&
3666 N0.getOperand(1).getOpcode() == ISD::Constant) {
3667 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3671 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3680 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3681 N0.getOpcode() == ISD::ANY_EXTEND ||
3682 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3683 N0.getOperand(0).getOpcode() == ISD::SHL &&
3684 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3686 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3688 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3693 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
3694 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
3695 N0.getOperand(0)->getOperand(0)),
3704 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3705 N0.getOperand(1).getOpcode() == ISD::Constant) {
3706 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3714 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3718 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3721 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
3726 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3732 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
3746 SDValue N0 = N->getOperand(0);
3748 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3750 EVT VT = N0.getValueType();
3758 return N0;
3761 return N0;
3767 return N0;
3770 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3779 N0.getOperand(0), DAG.getValueType(ExtVT));
3783 if (N1C && N0.getOpcode() == ISD::SRA) {
3784 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3787 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
3797 if (N0.getOpcode() == ISD::SHL) {
3799 N0.getOperand(1));
3818 getShiftAmountTy(N0.getOperand(0).getValueType()));
3819 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
3820 N0.getOperand(0), Amt);
3821 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
3839 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
3851 if (N0.getOpcode() == ISD::TRUNCATE &&
3852 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3853 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3854 N0.getOperand(0).hasOneUse() &&
3855 N0.getOperand(0).getOperand(1).hasOneUse() &&
3856 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3857 EVT LargeVT = N0.getOperand(0).getValueType();
3859 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3865 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3867 N0.getOperand(0).getOperand(0), Amt);
3878 if (DAG.SignBitIsZero(N0))
3879 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
3891 SDValue N0 = N->getOperand(0);
3893 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3895 EVT VT = N0.getValueType();
3903 return N0;
3909 return N0;
3916 if (N1C && N0.getOpcode() == ISD::SRL &&
3917 N0.getOperand(1).getOpcode() == ISD::Constant) {
3918 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3922 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3927 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3928 N0.getOperand(0).getOpcode() == ISD::SRL &&
3929 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3931 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3933 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3934 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3940 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
3941 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
3942 N0.getOperand(0)->getOperand(0),
3948 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3949 N0.getValueSizeInBits() <= 64) {
3950 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3951 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
3956 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3958 EVT SmallVT = N0.getOperand(0).getValueType();
3964 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
3965 N0.getOperand(0),
3978 if (N0.getOpcode() == ISD::SRA)
3979 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
3983 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3986 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
4004 SDValue Op = N0.getOperand(0);
4007 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4027 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
4086 SDValue N0 = N->getOperand(0);
4090 if (isa<ConstantSDNode>(N0))
4091 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4096 SDValue N0 = N->getOperand(0);
4100 if (isa<ConstantSDNode>(N0))
4101 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4106 SDValue N0 = N->getOperand(0);
4110 if (isa<ConstantSDNode>(N0))
4111 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4116 SDValue N0 = N->getOperand(0);
4120 if (isa<ConstantSDNode>(N0))
4121 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4126 SDValue N0 = N->getOperand(0);
4130 if (isa<ConstantSDNode>(N0))
4131 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4136 SDValue N0 = N->getOperand(0);
4139 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4143 EVT VT0 = N0.getValueType();
4156 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4167 N0, DAG.getConstant(1, VT0));
4168 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4169 N0, DAG.getConstant(1, VT0));
4177 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4183 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4189 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4192 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4193 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4196 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4197 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4204 if (N0.getOpcode() == ISD::SETCC) {
4212 N0.getOperand(0), N0.getOperand(1),
4213 N1, N2, N0.getOperand(2));
4214 N0, N1, N2);
4221 SDValue N0 = N->getOperand(0);
4231 if (N0.getOpcode() == ISD::SETCC) {
4232 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4233 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4261 SDValue N0 = N->getOperand(0);
4273 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
4274 N0, N1, CC, SDLoc(N), false);
4297 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
4310 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4315 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4316 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4317 UE = N0.getNode()->use_end();
4322 if (UI.getUse().getResNo() != N0.getResNo())
4333 if (UseOp == N0)
4393 SDValue N0 = N->getOperand(0);
4397 if (isa<ConstantSDNode>(N0))
4398 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N0);
4402 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4404 N0.getOperand(0));
4406 if (N0.getOpcode() == ISD::TRUNCATE) {
4409 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4411 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4412 if (NarrowLoad.getNode() != N0.getNode()) {
4413 CombineTo(N0.getNode(), NarrowLoad);
4422 SDValue Op = N0.getOperand(0);
4424 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4447 N0.getValueType())) {
4449 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
4451 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
4453 DAG.getValueType(N0.getValueType()));
4461 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4462 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4463 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4466 if (!N0.hasOneUse())
4467 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4469 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4473 N0.getValueType(),
4477 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4478 N0.getValueType(), ExtLoad);
4479 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4488 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4489 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4490 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4501 CombineTo(N0.getNode(),
4502 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4503 N0.getValueType(), ExtLoad),
4511 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4512 N0.getOpcode() == ISD::XOR) &&
4513 isa<LoadSDNode>(N0.getOperand(0)) &&
4514 N0.getOperand(1).getOpcode() == ISD::Constant &&
4515 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4516 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4517 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4521 if (!N0.hasOneUse())
4522 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4532 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4534 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4537 SDLoc(N0.getOperand(0)),
4538 N0.getOperand(0).getValueType(), ExtLoad);
4540 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4548 if (N0.getOpcode() == ISD::SETCC) {
4554 EVT N0VT = N0.getOperand(0).getValueType();
4566 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4567 N0.getOperand(1),
4568 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4576 N0.getOperand(0), N0.getOperand(1),
4577 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4587 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
4589 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4597 N0.getOperand(0), N0.getOperand(1),
4598 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4605 DAG.SignBitIsZero(N0))
4606 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4650 SDValue N0 = N->getOperand(0);
4654 if (isa<ConstantSDNode>(N0))
4655 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4658 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4660 N0.getOperand(0));
4668 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4670 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4673 N0.getValueSizeInBits(),
4688 if (N0.getOpcode() == ISD::TRUNCATE) {
4689 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4691 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4692 if (NarrowLoad.getNode() != N0.getNode()) {
4693 CombineTo(N0.getNode(), NarrowLoad);
4702 if (N0.getOpcode() == ISD::TRUNCATE &&
4707 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4709 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4710 if (NarrowLoad.getNode() != N0.getNode()) {
4711 CombineTo(N0.getNode(), NarrowLoad);
4718 SDValue Op = N0.getOperand(0);
4727 N0.getValueType().getScalarType());
4732 if (N0.getOpcode() == ISD::AND &&
4733 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4734 N0.getOperand(1).getOpcode() == ISD::Constant &&
4735 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4736 N0.getValueType()) ||
4737 !TLI.isZExtFree(N0.getValueType(), VT))) {
4738 SDValue X = N0.getOperand(0).getOperand(0);
4744 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4754 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4755 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4756 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4759 if (!N0.hasOneUse())
4760 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4762 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4766 N0.getValueType(),
4770 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4771 N0.getValueType(), ExtLoad);
4772 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4782 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4783 N0.getOpcode() == ISD::XOR) &&
4784 isa<LoadSDNode>(N0.getOperand(0)) &&
4785 N0.getOperand(1).getOpcode() == ISD::Constant &&
4786 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4787 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4788 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4792 if (!N0.hasOneUse())
4793 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4803 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4805 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4808 SDLoc(N0.getOperand(0)),
4809 N0.getOperand(0).getValueType(), ExtLoad);
4811 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4821 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4822 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4823 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4834 CombineTo(N0.getNode(),
4835 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
4842 if (N0.getOpcode() == ISD::SETCC) {
4846 EVT N0VT = N0.getOperand(0).getValueType();
4857 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4858 N0.getOperand(1),
4859 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4873 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
4874 N0.getOperand(1),
4875 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4884 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
4886 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4891 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4892 isa<ConstantSDNode>(N0.getOperand(1)) &&
4893 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4894 N0.hasOneUse()) {
4895 SDValue ShAmt = N0.getOperand(1);
4897 if (N0.getOpcode() == ISD::SHL) {
4898 SDValue InnerZExt = N0.getOperand(0);
4913 return DAG.getNode(N0.getOpcode(), DL, VT,
4914 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4922 SDValue N0 = N->getOperand(0);
4926 if (isa<ConstantSDNode>(N0))
4927 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, N0);
4931 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4932 N0.getOpcode() == ISD::ZERO_EXTEND ||
4933 N0.getOpcode() == ISD::SIGN_EXTEND)
4934 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
4938 if (N0.getOpcode() == ISD::TRUNCATE) {
4939 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4941 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4942 if (NarrowLoad.getNode() != N0.getNode()) {
4943 CombineTo(N0.getNode(), NarrowLoad);
4952 if (N0.getOpcode() == ISD::TRUNCATE) {
4953 SDValue TruncOp = N0.getOperand(0);
4963 if (N0.getOpcode() == ISD::AND &&
4964 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4965 N0.getOperand(1).getOpcode() == ISD::Constant &&
4966 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4967 N0.getValueType())) {
4968 SDValue X = N0.getOperand(0).getOperand(0);
4974 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4984 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4985 N0)->isVolatile()) ||
4986 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4989 if (!N0.hasOneUse())
4990 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4992 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4996 N0.getValueType(),
5000 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5001 N0.getValueType(), ExtLoad);
5002 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5012 if (N0.getOpcode() == ISD::LOAD &&
5013 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5014 N0.hasOneUse()) {
5015 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5023 CombineTo(N0.getNode(),
5024 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5025 N0.getValueType(), ExtLoad),
5030 if (N0.getOpcode() == ISD::SETCC) {
5034 EVT N0VT = N0.getOperand(0).getValueType();
5041 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5042 N0.getOperand(1),
5043 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5055 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5056 N0.getOperand(1),
5057 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5064 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5066 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5126 SDValue N0 = N->getOperand(0);
5142 N0 = SDValue(N, 0);
5143 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5159 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5160 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5164 N0 = N0.getOperand(0);
5166 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5171 if (!isa<LoadSDNode>(N0)) return SDValue();
5176 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5182 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5190 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5191 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5192 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5194 N0 = N0.getOperand(0);
5200 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5204 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5227 EVT PtrType = N0.getOperand(1).getValueType();
5250 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
5255 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
5262 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5277 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5286 SDValue N0 = N->getOperand(0);
5294 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5295 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5298 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5299 return N0;
5302 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5303 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
5305 N0.getOperand(0), N1);
5310 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5311 SDValue N00 = N0.getOperand(0);
5318 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5319 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
5335 if (N0.getOpcode() == ISD::SRL) {
5336 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5340 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5343 N0.getOperand(0), N0.getOperand(1));
5348 if (ISD::isEXTLoad(N0.getNode()) &&
5349 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5350 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5351 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5353 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5361 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5366 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5367 N0
5368 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5369 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5371 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5379 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5384 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5385 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5386 N0.getOperand(1), false);
5396 SDValue N0 = N->getOperand(0);
5401 if (N0.getValueType() == N->getValueType(0))
5402 return N0;
5404 if (isa<ConstantSDNode>(N0))
5405 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
5407 if (N0.getOpcode() == ISD::TRUNCATE)
5408 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5410 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5411 N0.getOpcode() == ISD::SIGN_EXTEND ||
5412 N0.getOpcode() == ISD::ANY_EXTEND) {
5413 if (N0.getOperand(0).getValueType().bitsLT(VT))
5415 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5416 N0.getOperand(0));
5417 if (N0.getOperand(0).getValueType().bitsGT(VT))
5419 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5422 return N0.getOperand(0);
5435 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5436 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5438 EVT VecTy = N0.getOperand(0).getValueType();
5439 EVT ExTy = N0.getValueType();
5448 SDValue EltNo = N0->getOperand(1);
5455 NVT, N0.getOperand(0));
5468 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
5469 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
5470 N0.getOperand(0).hasOneUse()) {
5472 SDValue BuildVect = N0.getOperand(0);
5502 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5509 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5516 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5522 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5523 SDValue X = N0.getOperand(i);
5607 SDValue N0 = N->getOperand(0);
5615 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5618 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5619 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5620 N0.getOperand(i).getOpcode() != ISD::Constant &&
5621 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5630 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5634 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5635 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
5651 if (N0.getOpcode() == ISD::BITCAST)
5653 N0.getOperand(0));
5657 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5659 !cast<LoadSDNode>(N0)->isVolatile() &&
5661 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5672 CombineTo(N0.getNode(),
5673 DAG.getNode(ISD::BITCAST, SDLoc(N0),
5674 N0.getValueType(), Load),
5683 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
5684 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
5685 N0.getNode()->hasOneUse() && VT.isInteger() &&
5686 !VT.isVector() && !N0.getValueType().isVector()) {
5687 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
5688 N0.getOperand(0));
5692 if (N0.getOpcode() == ISD::FNEG)
5695 assert(N0.getOpcode() == ISD::FABS);
5704 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5705 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5707 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5710 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5711 IntXVT, N0.getOperand(1));
5735 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5736 VT, N0.getOperand(0));
5746 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5747 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5896 SDValue N0 = N->getOperand(0);
5898 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5910 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
5913 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
5917 return N0;
5921 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
5925 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5927 GetNegatedExpression(N0, DAG, LegalOperations));
5931 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5932 isa<ConstantFPSDNode>(N0.getOperand(1)))
5933 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
5935 N0.getOperand(1), N1));
5950 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
5955 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
5964 if (N0.getOpcode() == ISD::FMUL) {
5965 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5966 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5969 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5978 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5989 N0.getOperand(1) == N1.getOperand(0)) {
5994 N0.getOperand(1), NewCFP);
6000 N0.getOperand(0) == N1.getOperand(0)) {
6005 N0.getOperand(0), NewCFP);
6014 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
6019 N0, NewCFP);
6023 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6028 N0, NewCFP);
6033 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
6034 N0.getOperand(0) == N0.getOperand(1) &&
6035 N1.getOperand(1) == N0.getOperand(0)) {
6044 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6045 N0.getOperand(0) == N0.getOperand(1) &&
6046 N1.getOperand(0) == N0.getOperand(0)) {
6055 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) {
6056 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6058 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6059 (N0.getOperand(0) == N1))
6068 N1.getOperand(0) == N0)
6070 N0, DAG.getConstantFP(3.0, VT));
6075 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6076 N0.getOperand(0) == N0.getOperand(1) &&
6078 N0.getOperand(0) == N1.getOperand(0))
6080 N0.getOperand(0),
6091 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6093 N0.getOperand(0), N0.getOperand(1), N1);
6099 N1.getOperand(0), N1.getOperand(1), N0);
6106 SDValue N0 = N->getOperand(0);
6108 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6121 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6125 return N0;
6136 return DAG.getNode(ISD::FADD, dl, VT, N0,
6144 if (N0 == N1)
6151 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
6155 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
6168 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6170 N0.getOperand(0), N0.getOperand(1),
6179 N1.getOperand(1), N0);
6182 if (N0.getOpcode() == ISD::FNEG &&
6183 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6184 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6185 SDValue N00 = N0.getOperand(0).getOperand(0);
6186 SDValue N01 = N0.getOperand(0).getOperand(1);
6197 SDValue N0 = N->getOperand(0);
6199 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6212 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6215 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6226 return N0;
6229 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6233 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6236 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6244 GetNegatedExpression(N0, DAG, LegalOperations),
6251 N1CFP && N0.getOpcode() == ISD::FMUL &&
6252 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6253 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
6255 N0.getOperand(1), N1));
6261 SDValue N0 = N->getOperand(0);
6264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6278 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6282 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6287 N0 == N2.getOperand(0) &&
6289 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6296 N0.getOpcode() == ISD::FMUL && N1CFP &&
6297 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6299 N0.getOperand(0),
6300 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6308 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6312 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6319 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2)
6320 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6326 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
6327 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6336 SDValue N0 = N->getOperand(0);
6338 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6351 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
6368 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
6373 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6381 GetNegatedExpression(N0, DAG, LegalOperations),
6390 SDValue N0 = N->getOperand(0);
6392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6398 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
6404 SDValue N0 = N->getOperand(0);
6406 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6411 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
6419 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6423 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
6430 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6431 N0.getOpcode() == ISD::FCOPYSIGN)
6433 N0.getOperand(0), N1);
6437 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6442 N0, N1.getOperand(1));
6448 N0, N1.getOperand(0));
6454 SDValue N0 = N->getOperand(0);
6455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6457 EVT OpVT = N0.getValueType();
6464 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6471 if (DAG.SignBitIsZero(N0))
6472 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6482 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6487 { N0.getOperand(0), N0.getOperand(1),
6489 N0.getOperand(2) };
6495 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6496 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6500 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6502 N0.getOperand(0).getOperand(2) };
6511 SDValue N0 = N->getOperand(0);
6512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6514 EVT OpVT = N0.getValueType();
6521 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6528 if (DAG.SignBitIsZero(N0))
6529 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6540 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6544 { N0.getOperand(0), N0.getOperand(1),
6546 N0.getOperand(2) };
6555 SDValue N0 = N->getOperand(0);
6556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6561 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
6567 SDValue N0 = N->getOperand(0);
6568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6573 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
6579 SDValue N0 = N->getOperand(0);
6581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6586 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
6589 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6590 return N0.getOperand(0);
6593 if (N0.getOpcode() == ISD::FP_ROUND) {
6596 N0
6597 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
6602 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6603 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
6604 N0.getOperand(0), N1);
6607 Tmp, N0.getOperand(1));
6614 SDValue N0 = N->getOperand(0);
6617 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6629 SDValue N0 = N->getOperand(0);
6630 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6640 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
6644 if (N0.getOpcode() == ISD::FP_ROUND
6645 && N0.getNode()->getConstantOperandVal(1) == 1) {
6646 SDValue In = N0.getOperand(0);
6650 In, N0.getOperand(1));
6655 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6656 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6657 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6658 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6662 N0.getValueType(),
6666 CombineTo(N0.getNode(),
6667 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
6668 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6677 SDValue N0 = N->getOperand(0);
6685 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6687 return GetNegatedExpression(N0, DAG, LegalOperations);
6691 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6693 N0.getNode()->hasOneUse() &&
6694 N0.getOperand(0).getValueType().isInteger()) {
6695 SDValue Int = N0.getOperand(0);
6698 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
6707 if (N0.getOpcode() == ISD::FMUL) {
6708 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6711 N0.getOperand(0),
6713 N0.getOperand(1)));
6720 SDValue N0 = N->getOperand(0);
6721 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6726 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
6732 SDValue N0 = N->getOperand(0);
6733 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6738 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
6744 SDValue N0 = N->getOperand(0);
6745 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6750 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
6756 SDValue N0 = N->getOperand(0);
6757 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6767 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6769 if (N0.getOpcode() == ISD::FABS)
6773 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6774 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
6779 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6780 N0.getOperand(0).getValueType().isInteger() &&
6781 !N0.getOperand(0).getValueType().isVector()) {
6782 SDValue Int = N0.getOperand(0);
6785 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7680 SDValue N0 = Value.getOperand(0);
7681 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7682 Chain == SDValue(N0.getNode(), 1)) {
7683 LoadSDNode *LD = cast<LoadSDNode>(N0);
7734 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
7750 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
9281 SDValue N0 = N->getOperand(0);
9286 EVT ConcatVT = N0.getOperand(0).getValueType();
9312 if (FirstElt < N0.getNumOperands())
9313 Ops.push_back(N0.getOperand(FirstElt));
9315 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
9318 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
9332 SDValue N0 = N->getOperand(0);
9335 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
9338 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
9344 if (N0 == N1) {
9351 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
9356 if (N0.getOpcode() == ISD::UNDEF) {
9385 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
9391 SDNode *V = N0.getNode();
9416 return N0;
9425 return N0;
9429 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
9433 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
9443 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
9446 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
9449 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
9598 SDValue N0 = N->getOperand(0);
9600 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9605 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9606 SDValue Op = N0.getOperand(i);
9611 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
9619 if (Ops.size() != N0.getNumOperands())
9623 N0.getValueType(), &Ops[0], Ops.size());
9626 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
9628 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9630 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9631 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9640 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
9641 N0.getValueType(),
9769 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9771 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
9783 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
9784 N0, N1, CC, DL, false);
9801 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9803 return DAG.getNode(ISD::FABS, DL, VT, N0);
9807 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9849 getSetCCResultType(N0.getValueType()),
9850 N0, N1, CC);
9869 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9870 EVT XType = N0.getValueType();
9879 getShiftAmountTy(N0.getValueType()));
9880 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
9881 XType, N0, ShCt);
9892 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
9893 XType, N0,
9895 getShiftAmountTy(N0.getValueType())));
9913 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9914 N0->getValueType(0) == VT &&
9917 SDValue AndLHS = N0->getOperand(0);
9918 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9925 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
9932 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
9940 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9952 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9956 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
9957 N0, N1, CC);
9965 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
9987 EVT XType = N0.getValueType();
9990 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
10000 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
10007 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
10008 XType, DAG.getConstant(0, XType), N0);
10009 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
10017 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
10019 getShiftAmountTy(N0.getValueType())));
10034 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
10038 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
10041 EVT XType = N0.getValueType();
10043 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
10044 N0,
10046 getShiftAmountTy(N0.getValueType())));
10047 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
10048 XType, N0, Shift);
10059 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
10064 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
