Lines Matching refs:Op
359 assert(NumParts == 1 && "No-op copy with multiple parts!");
820 // = op c3, ..., f2
1156 SDValue Op;
1158 Op = DAG.getConstantFP(0, EltVT);
1160 Op = DAG.getConstant(0, EltVT);
1161 Ops.assign(NumElements, Op);
1460 assert(Opc == Instruction::And && "Unknown merge op!");
2766 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2773 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2781 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2789 // FPTrunc is never a no-op cast, no need to check
2799 // FPExt is never a no-op cast, no need to check
2806 // FPToUI is never a no-op cast, no need to check
2813 // FPToSI is never a no-op cast, no need to check
2820 // UIToFP is never a no-op cast, no need to check
2827 // SIToFP is never a no-op cast, no need to check
2835 // We can either truncate, zero extend, or no-op, accordingly.
2843 // We can either truncate, zero extend, or no-op, accordingly.
2854 // either a BITCAST or a no-op.
3624 SDValue Op = getValue(I.getArgOperand(i));
3625 Ops.push_back(Op);
3678 /// Op = (Op & 0x007fffff) | 0x3f800000;
3680 /// where Op is the hexadecimal representation of floating point value.
3682 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3683 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3692 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3694 /// where Op is the hexadecimal representation of floating point value.
3696 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3698 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3716 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3718 if (Op.getValueType() == MVT::f32 &&
3726 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3814 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3819 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3821 if (Op.getValueType() == MVT::f32 &&
3823 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3910 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3915 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3917 if (Op.getValueType() == MVT::f32 &&
3919 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4005 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4010 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4012 if (Op.getValueType() == MVT::f32 &&
4014 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4093 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4098 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4100 if (Op.getValueType() == MVT::f32 &&
4102 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4106 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4188 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4390 Optional<MachineOperand> Op;
4393 Op = MachineOperand::CreateFI(FI);
4395 if (!Op && N.getNode()) {
4408 Op = MachineOperand::CreateReg(Reg, false);
4411 if (!Op) {
4415 Op = MachineOperand::CreateReg(VMI->second, false);
4418 if (!Op && N.getNode())
4423 Op = MachineOperand::CreateFI(FINode->getIndex());
4425 if (!Op)
4430 if (Op->isReg())
4434 Op->getReg(), Offset, Variable));
4438 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4741 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4744 setValue(&I, Op.getValue(0));
4745 DAG.setRoot(Op.getValue(1));
4968 SDValue Op = getRoot();
4971 &Op, 1);
5004 SDValue Op = getRoot();
5006 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5112 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5114 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5137 ISD::NodeType Op;
5140 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5141 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5142 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5143 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5144 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5145 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5151 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
6463 SDValue Op = SDValue(Args[i].Node.getNode(),
6506 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6525 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6611 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6617 SDValue Op = getNonRegisterValue(V);
6618 assert((Op.getOpcode() != ISD::CopyFromReg ||
6619 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6626 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
