Lines Matching refs:RegVT
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
1780 B.RegVT = VT.getSimpleVT();
1781 B.Reg = FuncInfo.CreateReg(B.RegVT);
1815 MVT VT = BB.RegVT;
5790 MVT RegVT = *PhysReg.second->vt_begin();
5791 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5793 RegVT, OpInfo.CallOperand);
5794 OpInfo.ConstraintVT = RegVT;
5795 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5800 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5802 RegVT, OpInfo.CallOperand);
5803 OpInfo.ConstraintVT = RegVT;
5810 MVT RegVT;
5823 RegVT = *RC->vt_begin();
5842 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5849 RegVT = *RC->vt_begin();
5851 ValueVT = RegVT;
5858 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6197 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6198 MatchedRegs.RegVTs.push_back(RegVT);
6202 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6761 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
6764 RegVT, VT, NULL, AssertOp);
6768 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
