Lines Matching defs:And
68 /// Generate a libcall taking the given operands as arguments and returning a
101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
264 /// constant and return true.
273 case ISD::AND:
300 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
318 // Search for the smallest integer type with free casts to and from
346 /// use this information to simplify Op, create a new simplified DAG node and
347 /// return true, returning the original and new nodes in Old and New. Otherwise,
348 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
393 case ISD::AND:
402 // If the LHS already has zeros where RHSC does, this and is dead.
414 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
421 // These bits cannot contribute to the result of the 'and'.
445 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
449 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
479 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
483 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
508 // If all of the demanded bits on one side are known, and all of the set
510 // into an AND, as we know the bits will be cleared.
517 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
553 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
559 // Only known if known in both the LHS and RHS.
570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
577 // Only known if known in both the LHS and RHS.
679 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
688 // If this is an arithmetic shift right and only the low-bit is set, we can
716 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
778 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
813 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
867 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
873 // Simplify the input, using demanded bit information, and compute the known
927 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
939 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
945 // If this is an FP->Int bitcast and if the sign bit is the only
973 // Add, Sub, and Mul don't demand any bits in positions beyond that
1003 /// in Mask are known to be either zero or one and return them in the
1067 /// and cc. If it is unable to simplify it, return a null SDValue.
1083 // Ensure that the constant occurs on the RHS, and fold constant
1091 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1132 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1134 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1149 } else if (N0->getOpcode() == ISD::AND) {
1177 // If the LHS is '(and load, const)', the RHS is 0,
1178 // the test is for equality or unsigned, and all 1 bits of the const are
1181 N0.getOpcode() == ISD::AND && C1 == 0 &&
1227 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1301 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1329 (N0.getOpcode() == ISD::AND &&
1334 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1345 assert(N0.getOpcode() == ISD::AND &&
1348 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1371 if (Op0.getOpcode() == ISD::AND &&
1376 Op0 = DAG.getNode(ISD::AND, dl, VT,
1380 Op0 = DAG.getNode(ISD::AND, dl, VT,
1473 N0.getOpcode() == ISD::AND)
1479 // Perform the xform if the AND RHS is a single bit.
1500 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1576 // If the comparison was an awkward floating-point == or != and one of
1709 // instruction and X+Z has other uses. It could be an induction variable
1710 // chain, and the transform would increase register pressure.
1755 // Note that where y is variable and is known to have at most
1758 if (N0.getOpcode() == ISD::AND)
1766 if (N1.getOpcode() == ISD::AND)
1793 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1800 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1830 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1949 // is possible and fine if either GV or C are missing.
2024 // otherwise keep searching and return the first class found
2056 /// assembly value into the specific constraints and their prefixes,
2057 /// and also tie in the associated operand values.
2058 /// If this returns an empty vector, and if the constraint string itself
2067 // Do a prepass over the constraints, canonicalizing them, and building up the
2158 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2212 // Check and hook up tied operands, choose constraint code to use.
2264 /// Examine constraint type and operand type and determine a weight value.
2266 /// and the current alternative constraint selected.
2288 /// Examine constraint type and operand type and determine a weight value.
2290 /// and the current alternative constraint selected.
2340 /// Other -> immediates and magic values
2351 /// 1) If there is an 'other' constraint, and if the operand is valid for
2405 /// ComputeConstraintToUse - Determines the constraint code and constraint
2407 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2423 // Labels and constants are handled elsewhere ('X' is the only thing
2499 // If d > 0 and m < 0, add the numerator
2505 // If d < 0 and m > 0, subtract the numerator.
2518 // Extract the sign bit and add it to the quotient
