Lines Matching refs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
14 #include "ARMBaseInstrInfo.h"
89 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
102 ScheduleHazardRecognizer *ARMBaseInstrInfo::
112 ScheduleHazardRecognizer *ARMBaseInstrInfo::
121 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
271 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
362 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
391 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
429 bool ARMBaseInstrInfo::
436 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
452 bool ARMBaseInstrInfo::
474 bool ARMBaseInstrInfo::
501 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
519 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
543 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
632 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
643 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
756 void ARMBaseInstrInfo::
893 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
941 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
947 void ARMBaseInstrInfo::
1084 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1132 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1138 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1249 void ARMBaseInstrInfo::
1278 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1293 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1386 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1463 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1484 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1527 bool ARMBaseInstrInfo::
1543 bool ARMBaseInstrInfo::
1568 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1604 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1664 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1685 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1783 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1809 const ARMBaseInstrInfo &TII) {
1951 bool ARMBaseInstrInfo::
2065 bool ARMBaseInstrInfo::
2273 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2634 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2644 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2788 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2829 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2864 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2904 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2933 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3281 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3372 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3585 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3635 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3653 bool ARMBaseInstrInfo::
3675 bool ARMBaseInstrInfo::
3690 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3700 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3735 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3825 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4030 unsigned ARMBaseInstrInfo::
4092 void ARMBaseInstrInfo::
4127 bool ARMBaseInstrInfo::hasNOP() const {
4131 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
