Lines Matching refs:MIB
225 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
227 const MachineInstrBuilder &MIB,
273 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
274 MachineInstr *MI = &*MIB;
280 AddDefaultPred(MIB);
287 AddDefaultT1CC(MIB);
289 AddDefaultCC(MIB);
291 return MIB;
678 MachineInstrBuilder MIB;
681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
684 MIB.addImm(Id);
685 AddOptionalDefs(MIB);
688 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
692 AddOptionalDefs(MIB);
698 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
702 AddOptionalDefs(MIB);
709 MachineInstrBuilder MIB;
712 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
717 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
722 AddOptionalDefs(MIB);
960 const MachineInstrBuilder &MIB,
978 MIB.addFrameIndex(FI);
984 MIB.addReg(0);
985 MIB.addImm(Imm);
987 MIB.addImm(Addr.Offset);
989 MIB.addMemOperand(MMO);
992 MIB.addReg(Addr.Base.Reg);
998 MIB.addReg(0);
999 MIB.addImm(Imm);
1001 MIB.addImm(Addr.Offset);
1004 AddOptionalDefs(MIB);
1093 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1095 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1213 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1216 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1502 MachineInstrBuilder MIB;
1503 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1508 MIB.addImm(Imm);
1509 AddOptionalDefs(MIB);
2172 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2174 AddOptionalDefs(MIB);
2176 MIB.addReg(RetRegs[i], RegState::Implicit);
2269 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2273 AddDefaultPred(MIB
2275 MIB.addReg(CalleeReg);
2277 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2281 MIB.addReg(RegArgs[i], RegState::Implicit);
2285 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2292 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2410 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2415 AddDefaultPred(MIB);
2417 MIB.addReg(CalleeReg);
2419 MIB.addGlobalAddress(GV, 0, 0);
2421 MIB.addExternalSymbol(IntrMemName, 0);
2425 MIB.addReg(RegArgs[i], RegState::Implicit);
2429 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2437 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2730 MachineInstrBuilder MIB = BuildMI(
2733 MIB.addReg(ARM::CPSR, RegState::Define);
2734 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2736 AddDefaultCC(MIB);
2808 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2813 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2815 MIB.addReg(Reg2);
2816 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2819 AddOptionalDefs(MIB);
2987 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2992 MIB.addImm(0);
2993 AddOptionalDefs(MIB);
