Lines Matching refs:v4i16
459 addDRTypeForNEON(MVT::v4i16);
549 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
551 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
561 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
562 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
582 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
609 // It is legal to extload from v4i8 to v4i16 or v4i32.
611 MVT::v4i16, MVT::v2i16,
931 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
3427 if (VT != MVT::v4i16)
3465 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3828 /// Trace for v4i16:
3849 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
3851 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
3854 /// Trace for v4i16:
3858 /// v4i16:Extracted = [k0 k1 k2 k3 ]
3866 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3898 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
3911 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
3923 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4165 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5387 return MVT::v4i16;
5601 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5638 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5644 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5656 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5658 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5660 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5662 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5665 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5666 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5679 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5691 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5693 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5695 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5697 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5700 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5701 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5712 // v4i16 sdiv ... Convert to float.
5747 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
