Lines Matching full:imm5
197 // t_addrmode_is4 := reg + imm5 * 4
209 // t_addrmode_is2 := reg + imm5 * 2
221 // t_addrmode_is1 := reg + imm5
572 // Loads: reg/reg and reg/imm5
584 def i : // reg/imm5
590 // Stores: reg/reg and reg/imm5
601 def i : // reg/imm5
896 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
898 "asr", "\t$Rd, $Rm, $imm5",
899 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
901 bits<5> imm5;
902 let Inst{10-6} = imm5;
981 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
983 "lsl", "\t$Rd, $Rm, $imm5",
984 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
986 bits<5> imm5;
987 let Inst{10-6} = imm5;
999 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1001 "lsr", "\t$Rd, $Rm, $imm5",
1002 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1004 bits<5> imm5;
1005 let Inst{10-6} = imm5;
