Lines Matching full:b0000
875 let Inst{7-4} = 0b0000;
1072 let Inst{26-23} = 0b0000;
1092 let Inst{26-23} = 0b0000;
1803 let Inst{7-4} = 0b0000;
2076 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2077 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2078 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2079 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2080 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2081 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2128 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2134 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2274 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2452 let Inst{7-4} = 0b0000; // Multiply
2463 let Inst{7-4} = 0b0000; // Multiply
2480 def t2SMULL : T2MulLong<0b000, 0b0000,
2485 def t2UMULL : T2MulLong<0b010, 0b0000,
2492 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2498 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2522 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2543 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2564 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2762 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2774 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2786 0, 0b010, 0b0000, (outs rGPR:$Rd),
2795 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
3024 defm t2TST : T2I_cmp_irs<0b0000, "tst",
3774 let Inst{7-0} = 0b0000;
3784 let Inst{7-0} = 0b0000;
