Lines Matching refs:Op
171 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
173 switch (Op.getOpcode()) {
175 Op.getNode()->dump();
180 case ISD::SDIV: return LowerSDIV(Op, DAG);
181 case ISD::SREM: return LowerSREM(Op, DAG);
182 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
183 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
185 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
186 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
188 return Op;
192 SDValue Op,
196 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
211 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
213 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
214 SDLoc DL(Op);
215 EVT VT = Op.getValueType();
218 default: return Op;
220 return LowerIntrinsicIABS(Op, DAG);
222 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
224 return LowerIntrinsicLRP(Op, DAG);
226 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
228 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
229 Op.getOperand(2));
231 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
232 Op.getOperand(2));
234 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
235 Op.getOperand(2));
237 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
238 Op.getOperand(2));
240 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
241 Op.getOperand(2));
243 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
244 Op.getOperand(2));
246 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
251 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
254 SDLoc DL(Op);
255 EVT VT = Op.getValueType();
257 Op.getOperand(1));
259 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
264 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
266 SDLoc DL(Op);
267 EVT VT = Op.getValueType();
270 Op.getOperand(1));
272 Op.getOperand(3));
274 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
279 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
281 SDLoc DL(Op);
282 EVT VT = Op.getValueType();
284 SDValue LHS = Op.getOperand(0);
285 SDValue RHS = Op.getOperand(1);
286 SDValue True = Op.getOperand(2);
287 SDValue False = Op.getOperand(3);
288 SDValue CC = Op.getOperand(4);
335 return Op;
340 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
342 SDLoc DL(Op);
343 EVT VT = Op.getValueType();
345 SDValue Num = Op.getOperand(0);
346 SDValue Den = Op.getOperand(1);
449 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
450 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
459 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
460 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
