Lines Matching refs:Op
247 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
248 // be zero. Op is expected to be a target specific node. Used by DAG
253 const SDValue Op,
261 switch (Op.getOpcode()) {
265 Op.getOperand(1),
271 Op.getOperand(0),
291 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
292 EVT OVT = Op.getValueType();
295 DST = LowerSDIV64(Op, DAG);
297 DST = LowerSDIV32(Op, DAG);
300 DST = LowerSDIV24(Op, DAG);
302 DST = SDValue(Op.getNode(), 0);
308 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
309 EVT OVT = Op.getValueType();
312 DST = LowerSREM64(Op, DAG);
314 DST = LowerSREM32(Op, DAG);
316 DST = LowerSREM16(Op, DAG);
318 DST = LowerSREM8(Op, DAG);
320 DST = SDValue(Op.getNode(), 0);
326 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const {
327 SDValue Data = Op.getOperand(0);
328 VTSDNode *BaseType = cast<VTSDNode>(Op.getOperand(1));
329 SDLoc DL(Op);
336 // If the op is less than 32 bits, then it needs to extend to 32bits
349 // Once the sign extension is done, the op needs to be converted to
351 Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
378 AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
379 SDValue Chain = Op.getOperand(0);
380 SDValue Cond = Op.getOperand(1);
381 SDValue Jump = Op.getOperand(2);
385 SDLoc(Op),
386 Op.getValueType(),
392 AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
393 SDLoc DL(Op);
394 EVT OVT = Op.getValueType();
395 SDValue LHS = Op.getOperand(0);
396 SDValue RHS = Op.getOperand(1);
473 AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
474 SDLoc DL(Op);
475 EVT OVT = Op.getValueType();
476 SDValue LHS = Op.getOperand(0);
477 SDValue RHS = Op.getOperand(1);
539 AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
540 return SDValue(Op.getNode(), 0);
544 AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const {
545 SDLoc DL(Op);
546 EVT OVT = Op.getValueType();
553 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
554 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
561 AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const {
562 SDLoc DL(Op);
563 EVT OVT = Op.getValueType();
570 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
571 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
578 AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
579 SDLoc DL(Op);
580 EVT OVT = Op.getValueType();
581 SDValue LHS = Op.getOperand(0);
582 SDValue RHS = Op.getOperand(1);
640 AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
641 return SDValue(Op.getNode(), 0);
