Lines Matching refs:Op
481 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
484 switch (Op.getOpcode()) {
485 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
487 case ISD::FSIN: return LowerTrig(Op, DAG);
488 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
489 case ISD::SELECT: return LowerSELECT(Op, DAG);
490 case ISD::STORE: return LowerSTORE(Op, DAG);
491 case ISD::LOAD: return LowerLOAD(Op, DAG);
492 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
493 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
495 SDValue Chain = Op.getOperand(0);
497 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
500 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
503 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
508 Op.getOperand(2), // Export Value
509 Op.getOperand(3), // ArrayBase
510 Op.getOperand(4), // Type
516 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
523 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
528 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
529 EVT VT = Op.getValueType();
530 SDLoc DL(Op);
532 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
534 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
544 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
545 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
627 Op.getOperand(1),
632 Op.getOperand(2),
633 Op.getOperand(3),
634 Op.getOperand(4),
639 Op.getOperand(5),
640 Op.getOperand(6),
641 Op.getOperand(7),
642 Op.getOperand(8),
643 Op.getOperand(9),
644 Op.getOperand(10)
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
660 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
662 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
664 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
708 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
711 } // end switch(Op.getOpcode())
738 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
741 EVT VT = Op.getValueType();
742 SDValue Arg = Op.getOperand(0);
743 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
744 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
745 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
749 switch (Op.getOpcode()) {
759 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
760 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
765 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
769 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
772 SDLoc(Op),
774 Op, DAG.getConstantFP(0.0f, MVT::f32),
795 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
801 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
809 bool R600TargetLowering::isZero(SDValue Op) const {
810 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
812 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
819 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
820 SDLoc DL(Op);
821 EVT VT = Op.getValueType();
823 SDValue LHS = Op.getOperand(0);
824 SDValue RHS = Op.getOperand(1);
825 SDValue True = Op.getOperand(2);
826 SDValue False = Op.getOperand(3);
827 SDValue CC = Op.getOperand(4);
909 SDValue MinMax = LowerMinMax(Op, DAG);
939 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
941 SDLoc(Op),
942 Op.getValueType(),
943 Op.getOperand(0),
945 Op.getOperand(1),
946 Op.getOperand(2),
1005 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1006 SDLoc DL(Op);
1007 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1008 SDValue Chain = Op.getOperand(0);
1009 SDValue Value = Op.getOperand(1);
1010 SDValue Ptr = Op.getOperand(2);
1115 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1117 EVT VT = Op.getValueType();
1118 SDLoc DL(Op);
1119 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1120 SDValue Chain = Op.getOperand(0);
1121 SDValue Ptr = Op.getOperand(1);
1221 Op.getOperand(2));
1232 Op.getOperand(2));
