Lines Matching refs:SITargetLowering
31 SITargetLowering::SITargetLowering(TargetMachine &TM) :
101 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
109 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT,
126 SDValue SITargetLowering::LowerFormalArguments(
271 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
327 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
334 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
342 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
422 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
498 SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
517 SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
532 SDValue SITargetLowering::LowerZERO_EXTEND(SDValue Op,
549 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
611 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
639 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
676 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
729 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
740 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
782 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
937 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1002 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1014 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1037 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1073 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
