Lines Matching refs:STORE
1513 setTargetDAGCombine(ISD::STORE);
1593 /// and store operations as a result of memset, memcpy, and memmove
2329 // registers, then we must store them to their spots on the stack so
2338 // Store the integer parameter registers.
2349 SDValue Store =
2354 MemOps.push_back(Store);
2359 // Now store the XMM (fp + vector) parameter registers.
2449 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2455 // Store the return address to the appropriate stack slot.
2594 // Store the argument.
2687 // than necessary, because it means that each store effectively depends
2721 // Store relative to framepointer.
2734 // Store the return address to the appropriate stack slot.
6466 // using a single extract together, load it and store it.
6968 // When V1 is a load, it can be folded later into a store in isel, example:
6969 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7504 // result has a single use which is a store or a bitcast to i32. And in
7505 // the case of a store, it's not worth it if the index is a constant 0,
7510 if ((User->getOpcode() != ISD::STORE ||
8607 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8622 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8702 // FIXME This causes a redundant load/store if the SSE-class value is already
9324 // selected as part of a load-modify-store instruction. When the root node
9325 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9337 UI->getOpcode() != ISD::STORE)
9391 // likely to be selected as part of a load-modify-store instruction.
9394 if (UI->getOpcode() == ISD::STORE)
10578 // Store gp_offset
10579 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10583 MemOps.push_back(Store);
10585 // Store fp_offset
10588 Store = DAG.getStore(Op.getOperand(0), DL,
10592 MemOps.push_back(Store);
10594 // Store ptr to overflow_arg_area
10599 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10602 MemOps.push_back(Store);
10604 // Store ptr to reg_save_area.
10609 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10611 MemOps.push_back(Store);
12699 // Convert seq_cst store -> xchg
12700 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12701 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12702 // (The only way to get a 16-byte store is cmpxchg16b)
13266 // by AM is legal for this target, for a load/store of the specified type.
14474 // Store it back into the va_list.
14530 // Store the new overflow address.
15059 // Store IP
15754 /// to a simple store and scalar loads to extract the elements.
15814 // Store the value to a temporary stack slot.
17472 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
17511 // Optimize trunc store (of multiple scalars) to shuffle and store.
17512 // First, pack all of the elements in one place. Next, store to memory
17524 // Accumulated smaller vector elements must be a multiple of the store size.
17552 // Find the largest store unit
17566 // Bitcast the original vector into a vector of store-size units
17592 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17597 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17616 // Must be a store of a load. We currently handle two cases: the load
17635 // If this is not the MMX case, i.e. we are just turning i64 load/store
17636 // into f64 load/store, avoid the transformation if there are multiple
17643 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17644 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18369 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18476 // Look out for (store (shl (load), x)).
