Lines Matching refs:v16f32
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
19013 case MVT::v16f32:
