Lines Matching full:i965
45 <li>New fragment shader back-end for i965-class hardware.
46 <li>Support for Sandybridge chipset in i965 DRI driver.
83 <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=31495">Bug 31495</a> - [i965 gles2c bisected] OpenGL ES 2.0 conformance GL2Tests_GetBIFD_input.run regressed</li>
105 <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=31909">Bug 31909</a> - [i965] brw_fs.cpp:1461: void fs_visitor::emit_bool_to_cond_code(ir_rvalue*): Assertion `expr->operands[i]->type->is_scalar()' failed.</li>
137 <li>i965: Update renderer strings for sandybridge</li>
1022 <li>i965: Share the KIL_NV implementation between glsl and non-glsl.</li>
1023 <li>i965: Also enable CC statistics when doing OQs.</li>
1024 <li>i965: Track the windowizer's dispatch for kill pixel, promoted, and OQ</li>
1028 <li>i965: Fix the vector/expression splitting for the write_mask change.</li>
1029 <li>i965: When splitting vector variable assignment, ignore unset channels.</li>
1030 <li>i965: Update expression splitting for the vector-result change to compares.</li>
1031 <li>i965: Warning fix for vector result any_nequal/all_equal change.</li>
1046 <li>i965: Add support for rendering to SARGB8 FBOs.</li>
1054 <li>i965: Fix up writemasked assignments in the new FS.</li>
1055 <li>i965: Remove swizzling of assignment to vector-splitting single-channel LHS.</li>
1056 <li>i965: Handle all_equal/any_nequal in the new FS.</li>
1057 <li>i965: Fix vector splitting RHS channel selection with sparse writemasks.</li>
1058 <li>i965: Add support for dFdx()/dFdy() to the FS backend.</li>
1059 <li>i965: Add support for attribute interpolation on Sandybridge.</li>
1060 <li>i965: Set up inputs to the fragment shader according to FP InputsRead.</li>
1061 <li>i965: Add support for POW in gen6 FS.</li>
1062 <li>i965: Fix negation in the new FS backend.</li>
1063 <li>i965: Actually track the "if" depth in loop in the new FS backend.</li>
1064 <li>i965: Apply the same set of lowering passes to new FS as to Mesa IR.</li>
1065 <li>i965: Fix valgrind complaint about base_ir for new FS debugging.</li>
1066 <li>i965: Fix up the FS backend for the variable array indexing pass.</li>
1067 <li>i965: Set the variable type when dereferencing an array.</li>
1068 <li>i965: Add support for dereferencing structs to the new FS backend.</li>
1069 <li>i965: Add support for struct, array, and matrix uniforms to FS backend.</li>
1070 <li>i965: Fix all non-snb regression in the snb attribute interpolation commit.</li>
1071 <li>i965: Fix up part of my Sandybridge attributes support patch.</li>
1072 <li>i965: Add support for gl_FrontFacing to the new FS backend.</li>
1073 <li>i965: Subtract instead of adding when computing y delta in new FS backend.</li>
1075 <li>i965: Set up sampler numbers in the FS backend.</li>
1076 <li>i965: Add support for non-color render target write data to new FS backend.</li>
1077 <li>i965: Add support for MRT to the new FS backend.</li>
1078 <li>i965: Add support for ir_loop counters to the new FS backend.</li>
1079 <li>i965: Add support for ARB_fragment_coord_conventions to the new FS backend.</li>
1081 <li>i965: Do interpolation for varying matrices and arrays in the FS backend.</li>
1082 <li>i965: Don't try to emit interpolation for unused varying slots.</li>
1083 <li>i965: Fix array indexing of arrays of matrices.</li>
1084 <li>i965: Clean up obsolete FINISHME comment.</li>
1086 <li>i965: Add support for builtin uniforms to the new FS backend.</li>
1087 <li>i965: Fix use of undefined mem_ctx in vector splitting.</li>
1089 <li>i965: Clean up the virtual GRF handling.</li>
1091 <li>i965: First cut at register allocation using graph coloring.</li>
1092 <li>i965: Add live interval analysis and hook it up to the register allocator.</li>
1093 <li>i965: Remove my "safety counter" code from loops.</li>
1094 <li>i965: Fix whole-structure/array assignment in new FS.</li>
1096 <li>i965: Fix new FS handling of builtin uniforms with packed scalars in structs.</li>
1098 <li>i965: Use the lowering pass for texture projection.</li>
1099 <li>i965: Split the gen4 and gen5 sampler handling apart.</li>
1100 <li>i965: Add gen6 attribute interpolation to new FS backend.</li>
1101 <li>i965: Fix the gen6 jump size for BREAK/CONT in new FS.</li>
1102 <li>i965: Also increment attribute location when skipping unused slots.</li>
1103 <li>i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS.</li>
1104 <li>i965: Add real support for pre-gen5 texture sampling to the new FS.</li>
1105 <li>i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4.</li>
1106 <li>i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.</li>
1107 <li>i965: When producing a single channel swizzle, don't make a temporary.</li>
1108 <li>i965: Add a sanity check for register allocation sizes.</li>
1109 <li>i965: Fix off-by-ones in handling the last members of register classes.</li>
1110 <li>i965: Don't try to emit code if we failed register allocation.</li>
1111 <li>i965: Add support for EXT_texture_swizzle to the new FS backend.</li>
1112 <li>i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.</li>
1113 <li>i965: Fix glean/texSwizzle regression in previous commit.</li>
1114 <li>i965: Be more conservative on live interval calculation.</li>
1115 <li>i965: Add trivial dead code elimination in the new FS backend.</li>
1116 <li>i965: Add initial folding of constants into operand immediate slots.</li>
1117 <li>i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.</li>
1118 <li>i965: Add support for gen6 FB writes to the new FS.</li>
1119 <li>i965: Enable the constant propagation code.</li>
1120 <li>i965: Also do constant propagation for the second operand of CMP.</li>
1121 <li>i965: Add back gen6 headerless FB writes to the new FS backend.</li>
1122 <li>i965: Gen6 no longer has the IFF instruction; always use IF.</li>
1123 <li>i965: Fix up IF/ELSE/ENDIF for gen6.</li>
1124 <li>i965: Fix botch in the header_present case in the new FS.</li>
1125 <li>i965: Add some clarification of the WECtrl field.</li>
1126 <li>i965: Don't do 1/w multiplication in new FS for gen6</li>
1127 <li>i965: Gen6's sampler messages are the same as Ironlake.</li>
1128 <li>i965: Refactor gl_FrontFacing setup out of general variable setup.</li>
1129 <li>i965: Add support for gl_FrontFacing on gen6.</li>
1130 <li>i965: Don't assume that WPOS is always provided on gen6 in the new FS.</li>
1131 <li>i965: Fix gen6 pointsize handling to match pre-gen6.</li>
1132 <li>i965: Disable emitting if () statements on gen6 until we really fix them.</li>
1133 <li>i965: Normalize cubemap coordinates like is done in the Mesa IR path.</li>
1135 <li>i965: Drop the check for duplicate _mesa_add_state_reference.</li>
1136 <li>i965: Drop the check for YUV constants in the param list.</li>
1137 <li>i965: Handle swizzles in the addition of YUV texture constants.</li>
1138 <li>i965: Fix gen6 WM push constants updates.</li>
1139 <li>i965: Fix new FS gen6 interpolation for sparsely-populated arrays.</li>
1140 <li>i965: Enable attribute swizzling (repositioning) in the gen6 SF.</li>
1141 <li>i965: Add register coalescing to the new FS backend.</li>
1142 <li>i965: Split FS_OPCODE_DISCARD into two steps.</li>
1143 <li>i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.</li>
1144 <li>i965: Move FS backend structures to a header.</li>
1145 <li>i965: Give the math opcodes information on base mrf/mrf len.</li>
1146 <li>i965: Give the FB write and texture opcodes the info on base MRF, like math.</li>
1147 <li>i965: Compute to MRF in the new FS backend.</li>
1148 <li>i965: Don't consider gen6 math instructions to write to MRFs.</li>
1149 <li>i965: Add a couple of checks for gen6 math instruction limits.</li>
1150 <li>i965: Don't compute-to-MRF in gen6 math instructions.</li>
1151 <li>i965: Expand uniform args to gen6 math to full registers to get hstride == 1.</li>
1152 <li>i965: Don't compute-to-MRF in gen6 VS math.</li>
1153 <li>i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.</li>
1154 <li>i965: Always use the new FS backend on gen6.</li>
1155 <li>i965: Fix missing "break;" in i2b/f2b, and missing AND of CMP result.</li>
1157 <li>i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.</li>
1158 <li>i965: Add support for rescaling GL_TEXTURE_RECTANGLE coords to new FS.</li>
1159 <li>i965: Set class_sizes[] for the aligned reg pair class.</li>
1160 <li>i965: Update the live interval when coalescing regs.</li>
1161 <li>i965: Add a pass to the FS to split virtual GRFs to float channels.</li>
1162 <li>i965: Add a function for handling the move of boolean values to flag regs.</li>
1163 <li>i965: Add peepholing of conditional mod generation from expressions.</li>
1164 <li>i965: Enable the new FS backend on pre-gen6 as well.</li>
1165 <li>i965: Fix texturing on pre-gen5.</li>
1166 i965: Set the type of the null register to fix gen6 FS comparisons.</li>
1167 <li>i965: Disable the debug printf I added for FS disasm.</li>
1168 <li>i965: Fix a weirdness in NOT handling.</li>
1169 <li>i965: Fix assertion failure on gen6 BufferSubData to busy BO.</li>
1170 <li>i965: Assert out on gen6 VS constant buffer reads that hang the GPU for now.</li>
1171 <li>i965: Fix scissor-offscreen on gen6 like we did pre-gen6.</li>
1172 <li>i965: Avoid blits in BufferCopySubdata on gen6.</li>
1173 <li>i965: Tell the shader compiler when we expect depth writes for gen6.</li>
1174 <li>i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver.</li>
1175 <li>i965: Disable thread dispatch when the FS doesn't do any work.</li>
1176 <li>i965: Add EU emit support for gen6's new IF instruction with comparison.</li>
1177 <li>i965: Set the source operand types for gen6 if/else/endif to integer.</li>
1178 <li>i965: Use the new style of IF statement with embedded comparison on gen6.</li>
1179 <li>i965: Split register allocation out of the ever-growing brw_fs.cpp.</li>
1180 <li>i965: Fix gl_FrontFacing emit on pre-gen6.</li>
1181 <li>i965: Add support for register spilling.</li>
1182 <li>i965: Don't emit register spill offsets directly into g0.</li>
1183 <li>i965: Correct scratch space allocation.</li>
1184 <li>i965: Be more aggressive in tracking live/dead intervals within loops.</li>
1185 <li>i965: Move the FS disasm/annotation printout to codegen time.</li>
1186 <li>i965: Add support for pull constants to the new FS backend.</li>
1187 <li>i965: Add EU code for dword scattered reads (constant buffer array indexing).</li>
1188 <li>i965: Clarify an XXX comment in FB writes with real info.</li>
1189 <li>i965: Use SENDC on the first render target write on gen6.</li>
1190 <li>i965: Clear some undefined fields of g0 when using them for gen6 FB writes.</li>
1191 <li>i965: Add disasm for the flag register.</li>
1192 <li>i965: Add support for discard instructions on gen6.</li>
1193 <li>i965: Handle new ir_unop_round_even in channel expression splitting.</li>
1194 <li>i965: Fix typo in comment about state flags.</li>
1195 <li>i965: Set up the constant buffer on gen6 when it's needed.</li>
1196 <li>i965: Add support for constant buffer loads on gen6.</li>
1197 <li>i965: Drop the eot argument to read messages, which can never be set.</li>
1198 <li>i965: Fix VS URB entry sizing.</li>
1199 <li>i965: Disable register spilling on gen6 until it's fixed.</li>
1200 <li>i965: Make FS uniforms be the actual type of the uniform at upload time.</li>
1201 <li>i965: Add user clip planes support to gen6.</li>
1202 <li>i965: Update gen6 SF state when point state (sprite or attenuation) changes.</li>
1203 <li>i965: Upload required gen6 VS push constants even when using pull constants.</li>
1204 <li>i965: Update the gen6 stencil ref state when stencil state changes.</li>
1210 <li>i965: Remove dead intel_structs.h file.</li>
1217 <li>i965: Allow OPCODE_SWZ to put immediates in the first arg.</li>
1218 <li>i965: Add support for math on constants in gen6 brw_wm_glsl.c path.</li>
1219 <li>i965: Work around strangeness in swizzling/masking of gen6 math.</li>
1220 <li>i965: re-enable gen6 IF statements in the fragment shader.</li>
1222 <li>i965: Fix gl_FragCoord inversion when drawing to an FBO.</li>
1223 <li>i965: Shut up spurious gcc warning about GLSL_TYPE enums.</li>
1225 <li>i965: Add state dumping for sampler state.</li>
1226 <li>i965: Add dumping of the sampler default color.</li>
1227 <li>i965: Fail on loops on gen6 for now until we write the EU emit code for it.</li>
1228 <li>i965: Eliminate dead code more aggressively.</li>
1230 <li>i965: Fix compute_to_mrf to not move a MRF write up into another live range.</li>
1231 <li>i965: Just use memset() to clear most members in FS constructors.</li>
1232 <li>i965: Remove extra n at the end of every instruction in INTEL_DEBUG=wm.</li>
1233 <li>i965: Fold constants into the second arg of BRW_SEL as well.</li>
1235 <li>i965: Recognize saturates and turn them into a saturated mov.</li>
1237 <li>i965: Improve compute-to-mrf.</li>
1238 <li>i965: Remove duplicate MRF writes in the FS backend.</li>
1239 <li>i965: Move gen4 blend constant color to the gen4 blending file.</li>
1240 <li>i965: Don't upload polygon stipple unless required.</li>
1241 <li>i965: Don't upload line stipple pattern unless we're stippling.</li>
1242 <li>i965: Don't upload line smooth params unless we're line smoothing.</li>
1243 <li>i965: Use the new embedded compare in SEL on gen6 for VS MIN and MAX opcodes.</li>
1244 <li>i965: Fix type of gl_FragData[] dereference for FB write.</li>
1250 <li>i965: Dump the WHILE jump distance on gen6.</li>
1251 <li>i965: Add support for gen6 DO/WHILE ISA emit.</li>
1252 <li>i965: Add support for gen6 BREAK ISA emit.</li>
1253 <li>i965: Add support for gen6 CONTINUE instruction emit.</li>
1254 <li>i965: Enable IF statements in the VS.</li>
1255 <li>i965: Add support for loops in the VS.</li>
1261 <li>i965: Update gen6 WM state on compiled program change, not just FP change.</li>
1262 <li>i965: Update gen6 SF state on fragment program change too.</li>
1263 <li>i965: Fix compile warning about missing opcodes.</li>
1264 <li>i965: Move payload reg setup to compile, not lookup time.</li>
1265 <li>i965: Provide delta_xy reg to gen6 non-GLSL path PINTERP.</li>
1266 <li>i965: Fix up 16-wide gen6 FB writes after various refactoring.</li>
1267 <li>i965: Don't smash a group of coordinates doing gen6 16-wide sampler headers.</li>
1268 <li>i965: Fix gen6 interpolation setup for 16-wide.</li>
1269 <li>i965: Fix up gen6 samplers for their usage by brw_wm_emit.c</li>
1270 <li>i965: Make the sampler's implied move on gen6 be a raw move.</li>
1271 <li>i965: Align gen6 push constant size to dispatch width.</li>
1272 <li>i965: Add support for the instruction compression bits on gen6.</li>
1273 <li>i965: Nuke brw_wm_glsl.c.</li>
1274 <li>i965: Remove INTEL_DEBUG=glsl_force now that there's no brw_wm_glsl.c</li>
1275 <li>i965: Fix comment about gen6_wm_constants.</li>
1276 <li>i965: Handle saturates on gen6 math instructions.</li>
1277 <li>i965: Always hand the absolute value to RSQ.</li>
1278 <li>i965: Add disabled debug code for dumping out the WM constant payload.</li>
1279 <li>i965: Work around gen6 ignoring source modifiers on math instructions.</li>
1280 <li>i965: Fix flipped value of the not-embedded-in-if on gen6.</li>
1281 <li>i965: Don't try to store gen6 (float) blend constant color in bytes.</li>
1282 <li>i965: Set up the color masking for the first drawbuffer on gen6.</li>
1283 <li>i965: Set up the per-render-target blend state on gen6.</li>
1284 <li>i965: Set the render target index in gen6 fixed-function/ARB_fp path.</li>
1285 <li>i965: Use the new pixel mask location for gen6 ARB_fp KIL instructions.</li>
1286 <li>i965: Drop KIL_NV from the ff/ARB_fp path since it was only used for GLSL.</li>
1287 <li>i965: Drop push-mode reladdr constant loading and always use constant_map.</li>
1288 <li>i965: Fix VS constants regression pre-gen6.</li>
1289 <li>i965: Clean up VS constant buffer location setup.</li>
1290 <li>i965: Set up the correct texture border color state struct for Ironlake.</li>
1291 <li>i965: Set render_cache_read_write surface state bit on gen6 constant surfs.</li>
1292 <li>i965: remove unused variable since brw_wm_glsl.c removal.</li>
1296 <li>i965: Correct the dp_read message descriptor setup on g4x.</li>
1298 <li>i965: Fix ARL to work on gen6.</li>
1300 <li>i965: Fix gl_FragCoord.z setup on gen6.</li>
1301 <li>i965: Add support for using the BLT ring on gen6.</li>
1306 <li>i965: Avoid using float type for raw moves, to work around SNB issue.</li>
1307 <li>i965: Set the alternative floating point mode on gen6 VS and WM.</li>
1308 <li>i965: Add support for gen6 constant-index constant loading.</li>
1309 <li>i965: Add support for gen6 reladdr VS constant loading.</li>
1310 <li>i965: Improve the hacks for ARB_fp scalar^scalar POW on gen6.</li>
1311 <li>i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.</li>
1312 <li>i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.</li>
1313 <li>i965: Do lowering of array indexing of a vector in the FS.</li>
1456 <li>i965: Enable GL_ARB_texture_rg</li>
1495 <li>i965: Fix indentation after commit 3322fbaf</li>
1526 <li>i965: Correctly emit constants for aggregate types (array, matrix, struct)</li>
1914 <li>i965: Fix incorrect batchbuffer size in gen6 clip state command.</li>
1915 <li>i965: Use logical-not when emitting ir_unop_ceil.</li>
1918 <li>i965: Use RNDZ for ir_unop_trunc in the new FS.</li>
1919 <li>i965: Correctly emit the RNDZ instruction.</li>
1920 <li>i965: Clean up a warning in the old fragment backend.</li>
1923 <li>i965: Add support for ir_unop_round_even via the RNDE instruction.</li>
1927 <li>i965: Add missing "break" statement.</li>
1930 <li>i965: Remove unused variable.</li>
1941 <li>i965: Add bit operation support to the fragment shader backend.</li>
1998 <li>i965: Flatten if-statements beyond depth 16 on pre-gen6.</li>
1999 <li>i965: Internally enable GL_NV_blend_square on ES2.</li>
2018 <li>i965: Don't write mrf assignment for pointsize output</li>
2265 <li>dri/i965: remove duplicated include</li>
2447 <li>egl/i965: include inline_wrapper_sw_helper.h</li>
2562 <li>i965: Silence unused variable warning on non-debug builds.</li>
2563 <li>i965: Silence unused variable warning on non-debug builds.</li>
2564 <li>i965: Initialize member variables.</li>
2597 <li>i965: Silence uninitialized variable warning.</li>
2598 <li>i965: Silence uninitialized variable warning.</li>
2638 <li>i965: Silence uninitialized variable warning.</li>
2675 <li>i965: Silence uninitialized variable warning.</li>
2693 <li>i965: add support for polygon mode on Sandybridge.</li>
2694 <li>i965: fix for flat shading on Sandybridge</li>
2695 <li>i965: set minimum/maximum Point Width on Sandybridge</li>
2697 <li>i965: support for two-sided lighting on Sandybridge</li>
2698 <li>i965: fix register region description</li>
2699 <li>i965: use align1 access mode for instructions with execSize=1 in VS</li>
2700 <li>i965: don't spawn GS thread for LINELOOP on Sandybridge</li>
2701 <li>i965: use BLT to clear buffer if possible on Sandybridge</li>
2718 <li>i965: disasm quarter and write enable instruction control on sandybridge</li>
2719 <li>i965: new state dump for sandybridge</li>
2720 <li>i965: enable accumulator update in PS kernel too on sandybridge</li>
2721 <li>i965: Fix color interpolation on sandybridge</li>
2722 <li>i965: force zero in clipper to ignore RTAIndex on sandybridge</li>
2723 <li>i965: fix point size setting in header on sandybridge</li>
2724 <li>i965: ff sync message change for sandybridge</li>
2725 <li>i965: ignore quads for GS kernel on sandybridge</li>
2726 <li>i965: add sandybridge viewport state bo into validation list</li>
2727 <li>i965: VS use SPF mode on sandybridge for now</li>
2728 <li>i965: fix jump count on sandybridge</li>
2729 <li>i965: Fix sampler on sandybridge</li>
2730 <li>i965: fix const register count for sandybridge</li>
2731 <li>i965: Add all device ids for sandybridge</li>
2732 <li>i965: sandybridge pipe control workaround before write cache flush</li>
2733 <li>i965: only allow SIMD8 kernel on sandybridge now</li>
2734 <li>i965: don't do calculation for delta_xy on sandybridge</li>
2735 <li>i965: fix pixel w interpolation on sandybridge</li>
2736 <li>i965: enable polygon offset on sandybridge</li>
2737 <li>i965: fix scissor state on sandybridge</li>
2738 <li>i965: fix point sprite on sandybridge</li>
2739 <li>i965: fix occlusion query on sandybridge</li>
2740 <li>i965: fallback bitmap operation on sandybridge</li>
2741 <li>i965: Always set tiling for depth buffer on sandybridge</li>
2742 <li>i965: fallback lineloop on sandybridge for now</li>
2743 <li>Revert "i965: Always set tiling for depth buffer on sandybridge"</li>
2744 <li>i965: always set tiling for fbo depth buffer on sandybridge</li>
2745 <li>i965: Fix GS hang on Sandybridge</li>
2746 <li>Revert "i965: fallback lineloop on sandybridge for now"</li>
2747 <li>i965: refresh wm push constant also for BRW_NEW_FRAMENT_PROGRAM on gen6</li>
2748 <li>i965: fix dest type of 'endif' on sandybridge</li>
2749 <li>Revert "i965: VS use SPF mode on sandybridge for now"</li>
2750 <li>i965: also using align1 mode for math2 on sandybridge</li>
2751 <li>i965: Fix GS state uploading on Sandybridge</li>
2752 <li>i965: upload WM state for _NEW_POLYGON on sandybridge</li>
2753 <li>i965: Use MI_FLUSH_DW for blt ring flush on sandybridge</li>
2754 <li>i965: explicit tell header present for fb write on sandybridge</li>
2755 <li>i965: Fix occlusion query on sandybridge</li>
2756 <li>i965: Use last vertex convention for quad provoking vertex on sandybridge</li>
2757 <li>i965: Fix provoking vertex select in clip state for sandybridge</li>
2762 <li>i965: skip too small size mipmap</li>
