Lines Matching refs:Op
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
82 switch (Op.getOpcode()) {
84 Op.getNode()->dump();
89 case ISD::SDIV: return LowerSDIV(Op, DAG);
90 case ISD::SREM: return LowerSREM(Op, DAG);
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
93 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
98 return Op;
101 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
104 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
105 DebugLoc DL = Op.getDebugLoc();
106 EVT VT = Op.getValueType();
109 default: return Op;
111 return LowerIntrinsicIABS(Op, DAG);
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
117 return LowerIntrinsicLRP(Op, DAG);
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
122 Op.getOperand(2), Op.getOperand(3));
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
125 Op.getOperand(2));
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
128 Op.getOperand(2));
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
131 Op.getOperand(2));
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
134 Op.getOperand(2));
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
137 Op.getOperand(2));
139 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
140 Op.getOperand(2));
142 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
149 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
153 DebugLoc DL = Op.getDebugLoc();
154 EVT VT = Op.getValueType();
156 Op.getOperand(1));
158 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
163 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
166 DebugLoc DL = Op.getDebugLoc();
167 EVT VT = Op.getValueType();
170 Op.getOperand(1));
172 Op.getOperand(3));
173 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
174 Op.getOperand(2),
180 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
183 DebugLoc DL = Op.getDebugLoc();
184 EVT VT = Op.getValueType();
186 SDValue Num = Op.getOperand(0);
187 SDValue Den = Op.getOperand(1);
281 DAG.ReplaceAllUsesWith(Op.getValue(0).getNode(), &Div);
282 DAG.ReplaceAllUsesWith(Op.getValue(1).getNode(), &Rem);
284 return Op;
291 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const
293 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
296 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
302 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const
304 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
