Lines Matching refs:dw
97 GLuint dw = i915->state.Ctx[reg]; \
98 dw &= ~(mask); \
99 dw |= (set); \
100 dirty |= dw != i915->state.Ctx[reg]; \
101 i915->state.Ctx[reg] = dw; \
183 GLuint dw;
187 dw = i915->state.Ctx[I915_CTXREG_LIS6];
188 dw &= ~(S6_ALPHA_TEST_FUNC_MASK | S6_ALPHA_REF_MASK);
189 dw |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) |
191 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
192 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
240 GLuint dw;
249 dw = (a << 24) | (r << 16) | (g << 8) | b;
250 if (dw != i915->state.Blend[I915_BLENDREG_BLENDCOLOR1]) {
251 i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = dw;
356 GLuint dw;
360 dw = i915->state.Ctx[I915_CTXREG_LIS6];
361 dw &= ~S6_DEPTH_TEST_FUNC_MASK;
362 dw |= test << S6_DEPTH_TEST_FUNC_SHIFT;
363 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
365 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
373 GLuint dw;
380 dw = i915->state.Ctx[I915_CTXREG_LIS6];
382 dw |= S6_DEPTH_WRITE_ENABLE;
384 dw &= ~S6_DEPTH_WRITE_ENABLE;
385 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
387 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
570 GLuint mode, dw;
592 dw = i915->state.Ctx[I915_CTXREG_LIS4];
593 dw &= ~S4_CULLMODE_MASK;
594 dw |= mode;
595 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
596 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
786 GLuint dw;
798 dw = i915->state.Ctx[I915_CTXREG_LIS6];
800 dw |= S6_ALPHA_TEST_ENABLE;
802 dw &= ~S6_ALPHA_TEST_ENABLE;
803 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
804 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
826 dw = i915->state.Ctx[I915_CTXREG_LIS5];
828 dw |= S5_COLOR_DITHER_ENABLE;
830 dw &= ~S5_COLOR_DITHER_ENABLE;
831 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
832 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
838 dw = i915->state.Ctx[I915_CTXREG_LIS6];
844 dw |= S6_DEPTH_TEST_ENABLE;
846 dw &= ~S6_DEPTH_TEST_ENABLE;
847 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
848 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
866 dw = i915->state.Ctx[I915_CTXREG_LIS4];
868 dw |= S4_LINE_ANTIALIAS_ENABLE;
870 dw &= ~S4_LINE_ANTIALIAS_ENABLE;
871 if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
872 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
885 dw = i915->state.Ctx[I915_CTXREG_LIS5];
887 dw |= (S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
889 dw &= ~(S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
890 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
891 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
