Lines Matching refs:graduated
15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
40 event:0x16 counters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions
53 event:0x24 counters:0,2 um:zero minimum:500 name:JR_NON_31_INSNS : 36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict)
54 event:0x25 counters:0,2 um:zero minimum:500 name:BRANCH_INSNS : 37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches
55 event:0x26 counters:0,2 um:zero minimum:500 name:BRANCH_LIKELY_INSNS : 38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions
56 event:0x27 counters:0,2 um:zero minimum:500 name:COND_BRANCH_INSNS : 39-0 Conditional branches graduated
57 event:0x28 counters:0,2 um:zero minimum:500 name:INTEGER_INSNS : 40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB
58 event:0x29 counters:0,2 um:zero minimum:500 name:LOAD_INSNS : 41-0 Loads graduated including CP1 ans CP2 loads
59 event:0x2a counters:0,2 um:zero minimum:500 name:J_JAL_INSNS : 42-0 J/JAL graduated
60 event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB
61 event:0x2c counters:0,2 um:zero minimum:500 name:DSP_INSNS : 44-0 DSP instructions graduated
62 event:0x2d counters:0,2 um:zero minimum:500 name:DSP_BRANCH_INSNS : 45-0 DSP branch instructions graduated
63 event:0x2e counters:0,2 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 46-0 Uncached loads graduated
67 event:0x33 counters:0,2 um:zero minimum:500 name:SC_INSNS : 51-0 SC instructions graduated
68 event:0x34 counters:0,2 um:zero minimum:500 name:PREFETCH_INSNS : 52-0 Prefetch instructions graduated
69 event:0x35 counters:0,2 um:zero minimum:500 name:NO_INSN_CYCLES : 53-0 No instructions graduated cycles
70 event:0x36 counters:0,2 um:zero minimum:500 name:ONE_INSN_CYCLES : 54-0 One instruction graduated cycles
128 event:0x423 counters:1,3 um:zero minimum:500 name:CP1_CP2_LOAD_INSNS : 35-1 CP1/CP2 load instructions graduated
129 event:0x424 counters:1,3 um:zero minimum:500 name:MISPREDICTED_JR_31_INSNS : 36-1 jr $31 instructions graduated after mispredict
130 event:0x425 counters:1,3 um:zero minimum:500 name:CP1_CP2_COND_BRANCH_INSNS : 37-1 CP1/CP2 conditional branch instructions graduated
131 event:0x426 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_LIKELY_INSNS : 38-1 Mispredicted branch likely instructions graduated
132 event:0x427 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 39-1 Mispredicted branches graduated
133 event:0x428 counters:1,3 um:zero minimum:500 name:FPU_INSNS : 40-1 FPU instructions graduated
134 event:0x429 counters:1,3 um:zero minimum:500 name:STORE_INSNS : 41-1 Store instructions graduated including CP1 ans CP2 stores
135 event:0x42a counters:1,3 um:zero minimum:500 name:MIPS16_INSNS : 42-1 MIPS16 instructions graduated
136 event:0x42b counters:1,3 um:zero minimum:500 name:NT_MUL_DIV_INSNS : 43-1 Integer multiply/divide instructions graduated
137 event:0x42c counters:1,3 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 44-1 ALU-DSP graduated, result was saturated
138 event:0x42d counters:1,3 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 45-1 MDU-DSP graduated, result was saturated
139 event:0x42e counters:1,3 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 46-1 Uncached stores graduated
143 event:0x435 counters:1,3 um:zero minimum:500 name:LOAD_MISS_INSNS : 53-1 Cacheable load instructions that miss in the cache graduated
144 event:0x436 counters:1,3 um:zero minimum:500 name:TWO_INSNS_CYCLES : 54-1 Two instructions graduated cycles
145 event:0x437 counters:1,3 um:zero minimum:500 name:CP1_CP2_STORE_INSNS : 55-1 CP1/CP2 Store graduated
