Cross Reference: /external/oprofile/events/ppc64/power7/events

Lines Matching full:1000
24 event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Number of PowerPC instructions successfully dispatched.
26 event:0X0014 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Number of run instructions completed.
30 event:0X0020 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP2 : (Group 2 pm_branch1) The count value of a Branch and Count instruction was predicted
31 event:0X0021 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP2 : (Group 2 pm_branch1) The target address of a Branch to Link instruction was predicted by the link stack.
32 event:0X0022 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP2 : (Group 2 pm_branch1) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
33 event:0X0023 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP2 : (Group 2 pm_branch1) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
34 event:0X0024 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_branch1) Number of run instructions completed.
38 event:0X0030 counters:0 um:zero minimum:1000 name:PM_BR_PRED_GRP3 : (Group 3 pm_branch2) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
39 event:0X0031 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP3 : (Group 3 pm_branch2) A conditional branch instruction was predicted as taken or not taken.
40 event:0X0032 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP3 : (Group 3 pm_branch2) The count value of a Branch and Count instruction was predicted
41 event:0X0033 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP3 : (Group 3 pm_branch2) The target address of a Branch to Link instruction was predicted by the link stack.
42 event:0X0034 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_branch2) Number of run instructions completed.
46 event:0X0040 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP4 : (Group 4 pm_branch3) The Branch execution unit finished an instruction
47 event:0X0041 counters:1 um:zero minimum:1000 name:PM_BR_TAKEN_GRP4 : (Group 4 pm_branch3) A branch instruction was taken. This could have been a conditional branch or an unconditional branch
48 event:0X0042 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP4 : (Group 4 pm_branch3) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
49 event:0X0043 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP4 : (Group 4 pm_branch3) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
50 event:0X0044 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP4 : (Group 4 pm_branch3) Number of run instructions completed.
54 event:0X0050 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP5 : (Group 5 pm_branch4) A conditional branch instruction was incorrectly predicted as taken or not taken.  The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
55 event:0X0051 counters:1 um:zero minimum:1000 name:PM_BR_UNCOND_GRP5 : (Group 5 pm_branch4) An unconditional branch was executed.
56 event:0X0052 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP5 : (Group 5 pm_branch4) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
57 event:0X0053 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP5 : (Group 5 pm_branch4) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
58 event:0X0054 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP5 : (Group 5 pm_branch4) Number of run instructions completed.
62 event:0X0060 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP6 : (Group 6 pm_branch5) Both the condition (taken or not taken) and the target address of a branch instruction was predicted.
63 event:0X0061 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_TA_GRP6 : (Group 6 pm_branch5) Branch mispredict - taken/not taken and target
64 event:0X0062 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP6 : (Group 6 pm_branch5) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
65 event:0X0063 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP6 : (Group 6 pm_branch5) A conditional branch instruction was predicted as taken or not taken.
66 event:0X0064 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP6 : (Group 6 pm_branch5) Number of run instructions completed.
70 event:0X0070 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP7 : (Group 7 pm_branch6) The count value of a Branch and Count instruction was predicted
71 event:0X0071 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP7 : (Group 7 pm_branch6) The target address of a Branch to Link instruction was predicted by the link stack.
72 event:0X0072 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP7 : (Group 7 pm_branch6) A conditional branch instruction was predicted as taken or not taken.
73 event:0X0073 counters:3 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP7 : (Group 7 pm_branch6) The target address of a branch instruction was predicted.
74 event:0X0074 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP7 : (Group 7 pm_branch6) Number of run instructions completed.
78 event:0X0080 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP8 : (Group 8 pm_branch7) A conditional branch instruction was incorrectly predicted as taken or not taken.  The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
79 event:0X0081 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP8 : (Group 8 pm_branch7) A conditional branch instruction was predicted as taken or not taken.
80 event:0X0082 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP8 : (Group 8 pm_branch7) The count value of a Branch and Count instruction was predicted
81 event:0X0083 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP8 : (Group 8 pm_branch7) The target address of a Branch to Link instruction was predicted by the link stack.
82 event:0X0084 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP8 : (Group 8 pm_branch7) Number of run instructions completed.
86 event:0X0090 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP9 : (Group 9 pm_branch8) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
87 event:0X0091 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP9 : (Group 9 pm_branch8) A conditional branch instruction was predicted as taken or not taken.
88 event:0X0092 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP9 : (Group 9 pm_branch8) The count value of a Branch and Count instruction was predicted
89 event:0X0093 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP9 : (Group 9 pm_branch8) The target address of a Branch to Link instruction was predicted by the link stack.
90 event:0X0094 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP9 : (Group 9 pm_branch8) Number of run instructions completed.
94 event:0X00A0 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP10 : (Group 10 pm_branch9) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
95 event:0X00A1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP10 : (Group 10 pm_branch9) A conditional branch instruction was predicted as taken or not taken.
96 event:0X00A2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP10 : (Group 10 pm_branch9) The count value of a Branch and Count instruction was predicted
97 event:0X00A3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP10 : (Group 10 pm_branch9) The target address of a Branch to Link instruction was predicted by the link stack.
98 event:0X00A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP10 : (Group 10 pm_branch9) Number of run instructions completed.
102 event:0X00B0 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP11 : (Group 11 pm_slb_miss) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
103 event:0X00B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP11 : (Group 11 pm_slb_miss) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
104 event:0X00B2 counters:2 um:zero minimum:1000 name:PM_ISLB_MISS_GRP11 : (Group 11 pm_slb_miss) A SLB miss for an instruction fetch as occurred
105 event:0X00B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP11 : (Group 11 pm_slb_miss) Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.
106 event:0X00B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP11 : (Group 11 pm_slb_miss) Number of run instructions completed.
110 event:0X00C0 counters:0 um:zero minimum:1000 name:PM_BTAC_MISS_GRP12 : (Group 12 pm_tlb_miss) BTAC Mispredicted
111 event:0X00C1 counters:1 um:zero minimum:1000 name:PM_TLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Total of Data TLB mises + Instruction TLB misses
112 event:0X00C2 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Data TLB misses, all page sizes.
113 event:0X00C3 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP12 : (Group 12 pm_tlb_miss) A TLB miss for an Instruction Fetch has occurred
114 event:0X00C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP12 : (Group 12 pm_tlb_miss) Number of run instructions completed.
118 event:0X00D0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_16G_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.
119 event:0X00D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.
120 event:0X00D2 counters:2 um:zero minimum:1000
121 event:0X00D3 counters:3 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.
122 event:0X00D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP13 : (Group 13 pm_dtlb_miss) Number of run instructions completed.
126 event:0X00E0 counters:0 um:zero minimum:1000 name:PM_DERAT_MISS_4K_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
127 event:0X00E1 counters:1 um:zero minimum:1000 name:PM_DERAT_MISS_64K_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
128 event:0X00E2 counters:2 um:zero minimum:1000 name:PM_DERAT_MISS_16M_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
129 event:0X00E3 counters:3 um:zero minimum:1000 name:PM_DERAT_MISS_16G_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
130 event:0X00E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP14 : (Group 14 pm_derat_miss1) Number of run instructions completed.
135 event:0X00F1 counters:1 um:zero minimum:1000 name:PM_DERAT_MISS_64K_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
136 event:0X00F2 counters:2 um:zero minimum:1000 name:PM_DERAT_MISS_16M_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
137 event:0X00F3 counters:3 um:zero minimum:1000 name:PM_DERAT_MISS_16G_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
138 event:0X00F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP15 : (Group 15 pm_derat_miss2) Number of run instructions completed.
142 event:0X0100 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP16 : (Group 16 pm_misc_miss1) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
143 event:0X0101 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP16 : (Group 16 pm_misc_miss1) The processor's Data Cache was reloaded but not from the local L2.
144 event:0X0102 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP16 : (Group 16 pm_misc_miss1) Total D-ERAT Misses.  Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.  Combined Unit 0 + 1.
145 event:0X0103 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP16 : (Group 16 pm_misc_miss1) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
146 event:0X0104 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP16 : (Group 16 pm_misc_miss1) Number of run instructions completed.
151 event:0X0111 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP17 : (Group 17 pm_misc_miss2)  Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
152 event:0X0112 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP17 : (Group 17 pm_misc_miss2) Total D-ERAT Misses.  Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.  Combined Unit 0 + 1.
153 event:0X0113 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP17 : (Group 17 pm_misc_miss2) Number of run instructions completed.
154 event:0X0114 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP17 : (Group 17 pm_misc_miss2) Number of run instructions completed.
159 event:0X0121 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP18 : (Group 18 pm_misc_miss3)  Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
160 event:0X0122 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP18 : (Group 18 pm_misc_miss3) Total D-ERAT Misses.  Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.  Combined Unit 0 + 1.
161 event:0X0123 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP18 : (Group 18 pm_misc_miss3) A Page Table Entry was loaded into the TLB but not from the local L2.
162 event:0X0124 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP18 : (Group 18 pm_misc_miss3) Number of run instructions completed.
166 event:0X0130 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP19 : (Group 19 pm_misc_miss4) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
167 event:0X0131 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP19 : (Group 19 pm_misc_miss4) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
169 event:0X0133 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP19 : (Group 19 pm_misc_miss4) Number of run instructions completed.
170 event:0X0134 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP19 : (Group 19 pm_misc_miss4) Number of run instructions completed.
174 event:0X0140 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP20 : (Group 20 pm_misc_miss5) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
175 event:0X0141 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP20 : (Group 20 pm_misc_miss5) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
176 event:0X0142 counters:2 um:zero minimum:1000 name:PM_ISLB_MISS_GRP20 : (Group 20 pm_misc_miss5) A SLB miss for an instruction fetch as occurred
178 event:0X0144 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP20 : (Group 20 pm_misc_miss5) Number of run instructions completed.
182 event:0X0150 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP21 : (Group 21 pm_pteg1) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
183 event:0X0151 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L3_GRP21 : (Group 21 pm_pteg1) Instruction PTEG loaded from L3
184 event:0X0152 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L21_MOD_GRP21 : (Group 21 pm_pteg1) PTEG loaded from another L2 on same chip modified
185 event:0X0153 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DL2L3_MOD_GRP21 : (Group 21 pm_pteg1) Instruction PTEG loaded from distant L2 or L3 modified
186 event:0X0154 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP21 : (Group 21 pm_pteg1) Number of run instructions completed.
190 event:0X0160 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from L2
191 event:0X0161 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RL2L3_SHR_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from remote L2 or L3 shared
192 event:0X0162 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DL2L3_SHR_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from remote L2 or L3 shared
193 event:0X0163 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_MOD_GRP22 : (Group 22 pm_pteg2) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a demand load or store.
194 event:0X0164 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP22 : (Group 22 pm_pteg2) Number of run instructions completed.
198 event:0X0170 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L31_MOD_GRP23 : (Group 23 pm_pteg3) PTEG loaded from another L3 on same chip modified
199 event:0X0171 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP23 : (Group 23 pm_pteg3)  Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
200 event:0X0172 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RMEM_GRP23 : (Group 23 pm_pteg3) Instruction PTEG loaded from remote memory
201 event:0X0173 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP23 : (Group 23 pm_pteg3) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
202 event:0X0174 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP23 : (Group 23 pm_pteg3) Number of run instructions completed.
206 event:0X0180 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RL2L3_MOD_GRP24 : (Group 24 pm_pteg4) Instruction PTEG loaded from remote L2 or L3 modified
207 event:0X0181 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_DMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.
208 event:0X0182 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
209 event:0X0183 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
210 event:0X0184 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP24 : (Group 24 pm_pteg4) Number of run instructions completed.
214 event:0X0190 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_MOD_GRP25 : (Group 25 pm_pteg5) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a remote module due to a demand load or store.
215 event:0X0191 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L31_SHR_GRP25 : (Group 25 pm_pteg5) PTEG loaded from another L3 on same chip shared
216 event:0X0192 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_SHR_GRP25 : (Group 25 pm_pteg5) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.
217 event:0X0193 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L21_SHR_GRP25 : (Group 25 pm_pteg5) PTEG loaded from another L2 on same chip shared
218 event:0X0194 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP25 : (Group 25 pm_pteg5) Number of run instructions completed.
222 event:0X01A0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_MOD_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from another L3 on same chip modified
223 event:0X01A1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DMEM_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from distant memory
224 event:0X01A2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_MOD_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from another L2 on same chip modified
225 event:0X01A3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_LMEM_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from local memory
226 event:0X01A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP26 : (Group 26 pm_pteg6) Number of run instructions completed.
230 event:0X01B0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_MOD_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L3 on same chip modified
231 event:0X01B1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_SHR_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L3 on same chip shared
232 event:0X01B2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_MOD_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L2 on same chip modified
233 event:0X01B3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_SHR_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L2 on same chip shared
234 event:0X01B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP27 : (Group 27 pm_pteg7) Number of run instructions completed.
238 event:0X01C0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L2
239 event:0X01C1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L3MISS_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L3 miss
240 event:0X01C2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RMEM_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from remote memory
241 event:0X01C3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2MISS_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L2 miss
242 event:0X01C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP28 : (Group 28 pm_pteg8) Number of run instructions completed.
246 event:0X01D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
247 event:0X01D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.
248 event:0X01D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
249 event:0X01D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB but not from the local L2.
250 event:0X01D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP29 : (Group 29 pm_pteg9) Number of run instructions completed.
254 event:0X01E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP30 : (Group 30 pm_pteg10) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
255 event:0X01E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP30 : (Group 30 pm_pteg10) A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.
258 event:0X01E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP30 : (Group 30 pm_pteg10) Number of run instructions completed.
262 event:0X01F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_MOD_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a remote module due to a demand load or store.
263 event:0X01F1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_SHR_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.
265 event:0X01F3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_MOD_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a demand load or store.
266 event:0X01F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP31 : (Group 31 pm_pteg11) Number of run instructions completed.
271 event:0X0201 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_DMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.
272 event:0X0202 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
273 event:0X0203 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
274 event:0X0204 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP32 : (Group 32 pm_pteg12) Number of run instructions completed.
278 event:0X0210 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP33 : (Group 33 pm_freq1) Power Management Event 1
279 event:0X0211 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP33 : (Group 33 pm_freq1) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
280 event:0X0212 counters:2 um:zero minimum:1000 name:PM_FREQ_DOWN_GRP33 : (Group 33 pm_freq1) Processor frequency was slowed down due to power management
281 event:0X0213 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP33 : (Group 33 pm_freq1) Processor frequency was sped up due to power management
282 event:0X0214 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP33 : (Group 33 pm_freq1) Number of run instructions completed.
286 event:0X0220 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP34 : (Group 34 pm_freq2) Power Management Event 1
287 event:0X0221 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP34 : (Group 34 pm_freq2) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
288 event:0X0222 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP34 : (Group 34 pm_freq2) Dispatch Held due to Thermal
289 event:0X0223 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP34 : (Group 34 pm_freq2) Processor frequency was sped up due to power management
290 event:0X0224 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP34 : (Group 34 pm_freq2) Number of run instructions completed.
294 event:0X0230 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_GRP35 : (Group 35 pm_L1_ref)  L1 D cache load references counted at finish
295 event:0X0231 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP35 : (Group 35 pm_L1_ref) Load references to Level 1 Data Cache, by unit 0.
296 event:0X0232 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP35 : (Group 35 pm_L1_ref) Load references to Level 1 Data Cache, by unit 1.
297 event:0X0233 counters:3 um:zero minimum:1000 name:PM_LSU_TWO_TABLEWALK_CYC_GRP35 : (Group 35 pm_L1_ref) Cycles when two tablewalks pending on this thread
298 event:0X0234 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP35 : (Group 35 pm_L1_ref) Number of run instructions completed.
302 event:0X0240 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_SYNC_GRP36 : (Group 36 pm_flush1) Dispatch Flush: Sync
303 event:0X0241 counters:1 um:zero minimum:1000 name:PM_FLUSH_DISP_TLBIE_GRP36 : (Group 36 pm_flush1) Dispatch Flush: TLBIE
304 event:0X0242 counters:2 um:zero minimum:1000 name:PM_FLUSH_DISP_SB_GRP36 : (Group 36 pm_flush1) Dispatch Flush: Scoreboard
305 event:0X0243 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP36 : (Group 36 pm_flush1) Flushes occurred including LSU and Branch flushes.
306 event:0X0244 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP36 : (Group 36 pm_flush1) Number of run instructions completed.
310 event:0X0250 counters:0 um:zero minimum:1000 name:PM_FLUSH_PARTIAL_GRP37 : (Group 37 pm_flush2) Partial flush
311 event:0X0251 counters:1 um:zero minimum:1000 name:PM_FLUSH_DISP_GRP37 : (Group 37 pm_flush2) Dispatch flush
312 event:0X0252 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP37 : (Group 37 pm_flush2) A flush was initiated by the Load Store Unit.
313 event:0X0253 counters:3 um:zero minimum:1000 name:PM_LSU_PARTIAL_CDF_GRP37 : (Group 37 pm_flush2) A partial cacheline was returned from the L3
314 event:0X0254 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP37 : (Group 37 pm_flush2) Number of run instructions completed.
318 event:0X0260 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_GRP38 : (Group 38 pm_flush) Dispatch flush
320 event:0X0262 counters:2 um:zero minimum:1000 name:PM_FLUSH_COMPLETION_GRP38 : (Group 38 pm_flush) Completion Flush
321 event:0X0263 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP38 : (Group 38 pm_flush) Flushes occurred including LSU and Branch flushes.
322 event:0X0264 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP38 : (Group 38 pm_flush) Number of run instructions completed.
326 event:0X0270 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP39 : (Group 39 pm_lsu_flush1) A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1).  Combined Unit 0 + 1.
327 event:0X0271 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP39 : (Group 39 pm_lsu_flush1) A store was flushed because it was unaligned (crossed a 4K boundary).  Combined Unit 0 + 1.
328 event:0X0272 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP39 : (Group 39 pm_lsu_flush1) Load Hit Load or Store Hit Load flush.  A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.  Combined Unit 0 + 1.
329 event:0X0273 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP39 : (Group 39 pm_lsu_flush1) Load Hit Store flush.  A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.  Combined Unit 0 + 1.
330 event:0X0274 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP39 : (Group 39 pm_lsu_flush1) Number of run instructions completed.
334 event:0X0280 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1).  Combined Unit 0 + 1.
335 event:0X0281 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)
336 event:0X0282 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).
337 event:0X0283 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP40 : (Group 40 pm_lsu_flush2) Flushes occurred including LSU and Branch flushes.
338 event:0X0284 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP40 : (Group 40 pm_lsu_flush2) Number of run instructions completed.
342 event:0X0290 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed because it was unaligned (crossed a 4K boundary).  Combined Unit 0 + 1.
343 event:0X0291 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).
344 event:0X0292 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)
345 event:0X0293 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP41 : (Group 41 pm_lsu_flush3) Flushes occurred including LSU and Branch flushes.
346 event:0X0294 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP41 : (Group 41 pm_lsu_flush3) Number of run instructions completed.
350 event:0X02A0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush.  A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.  Combined Unit 0 + 1.
351 event:0X02A1 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush.  A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
352 event:0X02A2 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush.  A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
353 event:0X02A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP42 : (Group 42 pm_lsu_flush4) Flushes occurred including LSU and Branch flushes.
354 event:0X02A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP42 : (Group 42 pm_lsu_flush4) Number of run instructions completed.
358 event:0X02B0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush.  A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.  Combined Unit 0 + 1.
359 event:0X02B1 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush.  A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.
360 event:0X02B2 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush.  A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.
361 event:0X02B3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP43 : (Group 43 pm_lsu_flush5) Flushes occurred including LSU and Branch flushes.
362 event:0X02B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP43 : (Group 43 pm_lsu_flush5) Number of run instructions completed.
366 event:0X02C0 counters:0 um:zero minimum:1000 name:PM_IC_DEMAND_CYC_GRP44 : (Group 44 pm_prefetch) Cycles when a demand ifetch was pending
367 event:0X02C1 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP44 : (Group 44 pm_prefetch) An instruction prefetch request has been made.
368 event:0X02C2 counters:2 um:zero minimum:1000 name:PM_IC_RELOAD_SHR_GRP44 : (Group 44 pm_prefetch) An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.
369 event:0X02C3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP44 : (Group 44 pm_prefetch) Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
370 event:0X02C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP44 : (Group 44 pm_prefetch) Number of run instructions completed.
374 event:0X02D0 counters:0 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP45 : (Group 45 pm_thread_cyc2) Cycles that both threads completed.
375 event:0X02D1 counters:1 um:zero minimum:1000 name:PM_THRD_ALL_RUN_CYC_GRP45 : (Group 45 pm_thread_cyc2) Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.
376 event:0X02D2 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP45 : (Group 45 pm_thread_cyc2) Instructions completed by this thread when both threads had their run latches set.
377 event:0X02D3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_0_1_CYC_GRP45 : (Group 45 pm_thread_cyc2)  Cycles thread running at priority level 0 or 1
378 event:0X02D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP45 : (Group 45 pm_thread_cyc2) Number of run instructions completed.
382 event:0X02E0 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_0_1_CYC_GRP46 : (Group 46 pm_thread_cyc5)  Cycles thread running at priority level 0 or 1
383 event:0X02E1 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_2_3_CYC_GRP46 : (Group 46 pm_thread_cyc5)  Cycles thread running at priority level 2 or 3
384 event:0X02E2 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_4_5_CYC_GRP46 : (Group 46 pm_thread_cyc5)  Cycles thread running at priority level 4 or 5
385 event:0X02E3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_6_7_CYC_GRP46 : (Group 46 pm_thread_cyc5)  Cycles thread running at priority level 6 or 7
386 event:0X02E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP46 : (Group 46 pm_thread_cyc5) Number of run instructions completed.
390 event:0X02F0 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 and FXU1 are both idle.
391 event:0X02F1 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP47 : (Group 47 pm_fxu1) Cycles when both FXU0 and FXU1 are busy.
392 event:0X02F2 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 is busy while FXU1 was idle
393 event:0X02F3 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 was idle while FXU1 was busy
394 event:0X02F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP47 : (Group 47 pm_fxu1) Number of run instructions completed.
398 event:0X0300 counters:0 um:zero minimum:1000 name:PM_FXU0_FIN_GRP48 : (Group 48 pm_fxu2) The Fixed Point unit 0 finished an instruction and produced a result.  Instructions that finish may not necessary complete.
401 event:0X0303 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP48 : (Group 48 pm_fxu2) The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.
402 event:0X0304 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP48 : (Group 48 pm_fxu2) Number of run instructions completed.
407 event:0X0311 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP49 : (Group 49 pm_fxu3) Cycles when both FXU0 and FXU1 are busy.
408 event:0X0312 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP49 : (Group 49 pm_fxu3) FXU0 is busy while FXU1 was idle
409 event:0X0313 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP49 : (Group 49 pm_fxu3) FXU0 was idle while FXU1 was busy
410 event:0X0314 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP49 : (Group 49 pm_fxu3) Number of run instructions completed.
414 event:0X0320 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP50 : (Group 50 pm_fxu4) FXU0 and FXU1 are both idle.
415 event:0X0321 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP50 : (Group 50 pm_fxu4) Cycles when both FXU0 and FXU1 are busy.
418 event:0X0324 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP50 : (Group 50 pm_fxu4) Number of run instructions completed.
422 event:0X0330 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_GRP51 : (Group 51 pm_L2_RCLD)  L2  RC load dispatch attempt
423 event:0X0331 counters:1 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_OTHER_GRP51 : (Group 51 pm_L2_RCLD)  L2  RC load dispatch attempt failed due to other reasons
424 event:0X0332 counters:2 um:zero minimum:1000 name:PM_L2_RCST_DISP_GRP51 : (Group 51 pm_L2_RCLD)  L2  RC store dispatch attempt
425 event:0X0333 counters:3 um:zero minimum:1000 name:PM_L2_RCLD_BUSY_RC_FULL_GRP51 : (Group 51 pm_L2_RCLD)  L2  activated Busy to the core for loads due to all RC full
426 event:0X0334 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP51 : (Group 51 pm_L2_RCLD) Number of run instructions completed.
430 event:0X0340 counters:0 um:zero minimum:1000 name:PM_L2_CO_FAIL_BUSY_GRP52 : (Group 52 pm_L2_RC)  L2  RC Cast Out dispatch attempt failed due to all CO machines busy
432 event:0X0342 counters:2 um:zero minimum:1000 name:PM_L2_RC_ST_DONE_GRP52 : (Group 52 pm_L2_RC) RC did st to line that was Tx or Sx
434 event:0X0344 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP52 : (Group 52 pm_L2_RC) Number of run instructions completed.
438 event:0X0350 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_GRP53 : (Group 53 pm_L2_RCST)  L2  RC load dispatch attempt
439 event:0X0351 counters:1 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_OTHER_GRP53 : (Group 53 pm_L2_RCST)  L2  RC load dispatch attempt failed due to other reasons
440 event:0X0352 counters:2 um:zero minimum:1000 name:PM_L2_RCST_DISP_FAIL_ADDR_GRP53 : (Group 53 pm_L2_RCST)  L2  RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
441 event:0X0353 counters:3 um:zero minimum:1000 name:PM_L2_RCST_DISP_FAIL_OTHER_GRP53 : (Group 53 pm_L2_RCST)  L2  RC store dispatch attempt failed due to other reasons
442 event:0X0354 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP53 : (Group 53 pm_L2_RCST) Number of run instructions completed.
446 event:0X0360 counters:0 um:zero minimum:1000 name:PM_L2_ST_GRP54 : (Group 54 pm_L2_ldst_1) Data Store Count
447 event:0X0361 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_GRP54 : (Group 54 pm_L2_ldst_1) Data Load Miss
450 event:0X0364 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP54 : (Group 54 pm_L2_ldst_1) Number of run instructions completed.
456 event:0X0372 counters:2 um:zero minimum:1000 name:PM_L2_LD_HIT_GRP55 : (Group 55 pm_L2_ldst_2) A load request (data or instruction) hit in the L2 directory.  Includes speculative, prefetched, and demand requests.  This event includes all requests to this L2 from all sources.  Total for all slices
457 event:0X0373 counters:3 um:zero minimum:1000 name:PM_L2_ST_HIT_GRP55 : (Group 55 pm_L2_ldst_2) A store request hit in the L2 directory.  This event includes all requests to this L2 from all sources. Total for all slices.
458 event:0X0374 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP55 : (Group 55 pm_L2_ldst_2) Number of run instructions completed.
464 event:0X0382 counters:2 um:zero minimum:1000 name:PM_L2_LD_DISP_GRP56 : (Group 56 pm_L2_ldst_3) All successful load dispatches
465 event:0X0383 counters:3 um:zero minimum:1000 name:PM_L2_ST_DISP_GRP56 : (Group 56 pm_L2_ldst_3) All successful store dispatches
466 event:0X0384 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP56 : (Group 56 pm_L2_ldst_3) Number of run instructions completed.
470 event:0X0390 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_ADDR_GRP57 : (Group 57 pm_L2_RCSTLD)  L2  RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
471 event:0X0391 counters:1 um:zero minimum:1000 name:PM_L2_RCST_BUSY_RC_FULL_GRP57 : (Group 57 pm_L2_RCSTLD)  L2  activated Busy to the core for stores due to all RC full
474 event:0X0394 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP57 : (Group 57 pm_L2_RCSTLD) Number of run instructions completed.
478 event:0X03A0 counters:0 um:zero minimum:1000 name:PM_PB_NODE_PUMP_GRP58 : (Group 58 pm_nest1)  Nest events (MC0/MC1/PB/GX), Pair0 Bit0
479 event:0X03A1 counters:1 um:zero minimum:1000 name:PM_PB_SYS_PUMP_GRP58 : (Group 58 pm_nest1)  Nest events (MC0/MC1/PB/GX), Pair1 Bit0
480 event:0X03A2 counters:2 um:zero minimum:1000 name:PM_PB_RETRY_NODE_PUMP_GRP58 : (Group 58 pm_nest1)  Nest events (MC0/MC1/PB/GX), Pair2 Bit0
481 event:0X03A3 counters:3 um:zero minimum:1000 name:PM_PB_RETRY_SYS_PUMP_GRP58 : (Group 58 pm_nest1)  Nest events (MC0/MC1/PB/GX), Pair3 Bit0
482 event:0X03A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP58 : (Group 58 pm_nest1) Number of run instructions completed.
486 event:0X03B0 counters:0 um:zero minimum:1000 name:PM_MEM0_RQ_DISP_GRP59 : (Group 59 pm_nest2)  Nest events (MC0/MC1/PB/GX), Pair0 Bit1
487 event:0X03B1 counters:1 um:zero minimum:1000 name:PM_MEM0_PREFETCH_DISP_GRP59 : (Group 59 pm_nest2)  Nest events (MC0/MC1/PB/GX), Pair1 Bit1
488 event:0X03B2 counters:2 um:zero minimum:1000 name:PM_MEM0_RD_CANCEL_TOTAL_GRP59 : (Group 59 pm_nest2)  Nest events (MC0/MC1/PB/GX), Pair2 Bit1
489 event:0X03B3 counters:3 um:zero minimum:1000 name:PM_MEM0_WQ_DISP_GRP59 : (Group 59 pm_nest2)  Nest events (MC0/MC1/PB/GX), Pair3 Bit1
490 event:0X03B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP59 : (Group 59 pm_nest2) Number of run instructions completed.
494 event:0X03C0 counters:0 um:zero minimum:1000 name:PM_NEST_PAIR0_ADD_GRP60 : (Group 60 pm_nest3)  Nest events (MC0/MC1/PB/GX), Pair0 ADD
495 event:0X03C1 counters:1 um:zero minimum:1000 name:PM_NEST_PAIR1_ADD_GRP60 : (Group 60 pm_nest3)  Nest events (MC0/MC1/PB/GX), Pair1 ADD
496 event:0X03C2 counters:2 um:zero minimum:1000 name:PM_NEST_PAIR2_ADD_GRP60 : (Group 60 pm_nest3)  Nest events (MC0/MC1/PB/GX), Pair2 ADD
497 event:0X03C3 counters:3 um:zero minimum:1000 name:PM_NEST_PAIR3_ADD_GRP60 : (Group 60 pm_nest3)  Nest events (MC0/MC1/PB/GX), Pair3 ADD
498 event:0X03C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP60 : (Group 60 pm_nest3) Number of run instructions completed.
502 event:0X03D0 counters:0 um:zero minimum:1000 name:PM_NEST_PAIR0_AND_GRP61 : (Group 61 pm_nest4)  Nest events (MC0/MC1/PB/GX), Pair0 AND
503 event:0X03D1 counters:1 um:zero minimum:1000 name:PM_NEST_PAIR1_AND_GRP61 : (Group 61 pm_nest4)  Nest events (MC0/MC1/PB/GX), Pair1 AND
504 event:0X03D2 counters:2 um:zero minimum:1000 name:PM_NEST_PAIR2_AND_GRP61 : (Group 61 pm_nest4)  Nest events (MC0/MC1/PB/GX), Pair2 AND
505 event:0X03D3 counters:3 um:zero minimum:1000 name:PM_NEST_PAIR3_AND_GRP61 : (Group 61 pm_nest4)  Nest events (MC0/MC1/PB/GX), Pair3 AND
506 event:0X03D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP61 : (Group 61 pm_nest4) Number of run instructions completed.
510 event:0X03E0 counters:0 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP62 : (Group 62 pm_L2_redir_pref) A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
511 event:0X03E1 counters:1 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP62 : (Group 62 pm_L2_redir_pref) A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
512 event:0X03E2 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_REQ_GRP62 : (Group 62 pm_L2_redir_pref) Demand Instruction fetch request
513 event:0X03E3 counters:3 um:zero minimum:1000 name:PM_IC_BANK_CONFLICT_GRP62 : (Group 62 pm_L2_redir_pref) Read blocked due to interleave conflict.
514 event:0X03E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP62 : (Group 62 pm_L2_redir_pref) Number of run instructions completed.
518 event:0X03F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP63 : (Group 63 pm_dlatencies1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
519 event:0X03F1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP63 : (Group 63 pm_dlatencies1) Number of PowerPC instructions successfully dispatched.
520 event:0X03F2 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP63 : (Group 63 pm_dlatencies1) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
521 event:0X03F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP63 : (Group 63 pm_dlatencies1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
522 event:0X03F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP63 : (Group 63 pm_dlatencies1) Number of run instructions completed.
526 event:0X0400 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP64 : (Group 64 pm_dlatencies2) The processor's Data Cache was reloaded from the local L3 due to a demand load.
528 event:0X0402 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP64 : (Group 64 pm_dlatencies2) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
530 event:0X0404 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP64 : (Group 64 pm_dlatencies2) Number of run instructions completed.
534 event:0X0410 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP65 : (Group 65 pm_dlatencies3) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load
535 event:0X0411 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP65 : (Group 65 pm_dlatencies3) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
536 event:0X0412 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP65 : (Group 65 pm_dlatencies3) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
538 event:0X0414 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP65 : (Group 65 pm_dlatencies3) Number of run instructions completed.
542 event:0X0420 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_GRP66 : (Group 66 pm_rejects1) The Load Store Unit rejected an instruction. Combined Unit 0 + 1
543 event:0X0421 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
544 event:0X0422 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
545 event:0X0423 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
546 event:0X0424 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP66 : (Group 66 pm_rejects1) Number of run instructions completed.
550 event:0X0430 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_GRP67 : (Group 67 pm_rejects2) The Load Store Unit rejected an instruction. Combined Unit 0 + 1
551 event:0X0431 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP67 : (Group 67 pm_rejects2) Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.
552 event:0X0432 counters:2 um:zero minimum:1000
553 event:0X0433 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP67 : (Group 67 pm_rejects2) The Store Request Queue is empty
554 event:0X0434 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP67 : (Group 67 pm_rejects2) Number of run instructions completed.
558 event:0X0440 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SET_MPRED_GRP68 : (Group 68 pm_rejects3) The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
559 event:0X0441 counters:1 um:zero minimum:1000 name:PM_LSU_SET_MPRED_GRP68 : (Group 68 pm_rejects3) Line already in cache at reload time
562 event:0X0444 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP68 : (Group 68 pm_rejects3) Number of run instructions completed.
566 event:0X0450 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.
567 event:0X0451 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all eight entries are full, subsequent load instructions are rejected.
568 event:0X0452 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries.  If all eight entries are full, subsequent load instructions are rejected.
570 event:0X0454 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP69 : (Group 69 pm_lsu_reject) Number of run instructions completed.
574 event:0X0460 counters:0 um:zero minimum:1000 name:PM_LSU_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed. Combined Unit 0 + 1.
575 event:0X0461 counters:1 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed by unit 0.
576 event:0X0462 counters:2 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed by Unit 0.
578 event:0X0464 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP70 : (Group 70 pm_lsu_ncld) Number of run instructions completed.
582 event:0X0470 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP71 : (Group 71 pm_gct1) Cycles when the Global Completion Table has no slots from this thread.
583 event:0X0471 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP71 : (Group 71 pm_gct1) Cycles when the Global Completion Table was completely empty.  No thread had an entry allocated.
584 event:0X0472 counters:2 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP71 : (Group 71 pm_gct1) The Global Completion Table is completely full.
586 event:0X0474 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP71 : (Group 71 pm_gct1) Number of run instructions completed.
590 event:0X0480 counters:0 um:zero minimum:1000 name:PM_GCT_UTIL_1_TO_2_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 1-2 entries
591 event:0X0481 counters:1 um:zero minimum:1000 name:PM_GCT_UTIL_3_TO_6_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 3-6 entries
592 event:0X0482 counters:2 um:zero minimum:1000 name:PM_GCT_UTIL_7_TO_10_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 7-10 entries
593 event:0X0483 counters:3 um:zero minimum:1000 name:PM_GCT_UTIL_11_PLUS_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 11+ entries
594 event:0X0484 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP72 : (Group 72 pm_gct2) Number of run instructions completed.
598 event:0X0490 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_MOD_GRP73 : (Group 73 pm_L2_castout_invalidate_1) An L2 line in the Modified state was castout. Total for all slices.
599 event:0X0491 counters:1 um:zero minimum:1000 name:PM_L2_DC_INV_GRP73 : (Group 73 pm_L2_castout_invalidate_1) The L2 invalidated a line in processor's data cache.  This is caused by the L2 line being cast out or invalidated. Total for all slices
602 event:0X0494 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP73 : (Group 73 pm_L2_castout_invalidate_1) Number of run instructions completed.
606 event:0X04A0 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_SHR_GRP74 : (Group 74 pm_L2_castout_invalidate_2) An L2 line in the Shared state was castout. Total for all slices.
607 event:0X04A1 counters:1 um:zero minimum:1000 name:PM_L2_IC_INV_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Icache Invalidates from L2
610 event:0X04A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Number of run instructions completed.
614 event:0X04B0 counters:0 um:zero minimum:1000 name:PM_DISP_HELD_GRP75 : (Group 75 pm_disp_held1) Dispatch Held
615 event:0X04B1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP75 : (Group 75 pm_disp_held1) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
616 event:0X04B2 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP75 : (Group 75 pm_disp_held1) Dispatch Held due to Thermal
617 event:0X04B3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP75 : (Group 75 pm_disp_held1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
618 event:0X04B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP75 : (Group 75 pm_disp_held1) Number of run instructions completed.
622 event:0X04C0 counters:0 um:zero minimum:1000 name:PM_THERMAL_WARN_GRP76 : (Group 76 pm_disp_held2) Processor in Thermal Warning
623 event:0X04C1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP76 : (Group 76 pm_disp_held2) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
624 event:0X04C2 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP76 : (Group 76 pm_disp_held2) Dispatch Held due to Thermal
625 event:0X04C3 counters:3 um:zero minimum:1000 name:PM_THERMAL_MAX_GRP76 : (Group 76 pm_disp_held2) The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.
626 event:0X04C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP76 : (Group 76 pm_disp_held2) Number of run instructions completed.
630 event:0X04D0 counters:0 um:zero minimum:1000 name:PM_DISP_CLB_HELD_BAL_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Balance
631 event:0X04D1 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_RES_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Resource
632 event:0X04D2 counters:2 um:zero minimum:1000 name:PM_DISP_CLB_HELD_TLBIE_GRP77 : (Group 77 pm_disp_clb_held) Dispatch Hold: Due to TLBIE
633 event:0X04D3 counters:3 um:zero minimum:1000 name:PM_DISP_CLB_HELD_SYNC_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Sync type instruction
634 event:0X04D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP77 : (Group 77 pm_disp_clb_held) Number of run instructions completed.
638 event:0X04E0 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP78 : (Group 78 pm_power) Power Management Event 1
639 event:0X04E1 counters:1 um:zero minimum:1000 name:PM_POWER_EVENT2_GRP78 : (Group 78 pm_power) Power Management Event 2
640 event:0X04E2 counters:2 um:zero minimum:1000 name:PM_POWER_EVENT3_GRP78 : (Group 78 pm_power) Power Management Event 3
641 event:0X04E3 counters:3 um:zero minimum:1000 name:PM_POWER_EVENT4_GRP78 : (Group 78 pm_power) Power Management Event 4
642 event:0X04E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP78 : (Group 78 pm_power) Number of run instructions completed.
646 event:0X04F0 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP79 : (Group 79 pm_dispatch1) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
647 event:0X04F1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP79 : (Group 79 pm_dispatch1) Number of PowerPC instructions successfully dispatched.
648 event:0X04F2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_GRP79 : (Group 79 pm_dispatch1) A group was dispatched
649 event:0X04F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP79 : (Group 79 pm_dispatch1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
650 event:0X04F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP79 : (Group 79 pm_dispatch1) Number of run instructions completed.
654 event:0X0500 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP80 : (Group 80 pm_dispatch2) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
657 event:0X0503 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP80 : (Group 80 pm_dispatch2) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
658 event:0X0504 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP80 : (Group 80 pm_dispatch2) Number of run instructions completed.
662 event:0X0510 counters:0 um:zero minimum:1000
663 event:0X0511 counters:1 um:zero minimum:1000 name:PM_IC_WRITE_ALL_GRP81 : (Group 81 pm_ic) Icache sectors written, prefetch + demand
664 event:0X0512 counters:2 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_ALL_GRP81 : (Group 81 pm_ic) Prefetch Canceled due to page boundary or icache hit
665 event:0X0513 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_ALL_GRP81 : (Group 81 pm_ic)  L2 I cache demand request due to BHT or redirect
666 event:0X0514 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP81 : (Group 81 pm_ic) Number of run instructions completed.
670 event:0X0520 counters:0 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_PAGE_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to page boundary
671 event:0X0521 counters:1 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_HIT_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to icache hit
672 event:0X0522 counters:2 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_L2_GRP82 : (Group 82 pm_ic_pref_cancel) L2 Squashed request
673 event:0X0523 counters:3 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_ALL_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to page boundary or icache hit
674 event:0X0524 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP82 : (Group 82 pm_ic_pref_cancel) Number of run instructions completed.
678 event:0X0530 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP83 : (Group 83 pm_ic_miss) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
679 event:0X0531 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP83 : (Group 83 pm_ic_miss) An instruction fetch request missed the L1 cache.
682 event:0X0534 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP83 : (Group 83 pm_ic_miss) Number of run instructions completed.
686 event:0X0540 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP84 : (Group 84 pm_cpi_stack1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
687 event:0X0541 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP84 : (Group 84 pm_cpi_stack1) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.
688 event:0X0542 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP84 : (Group 84 pm_cpi_stack1) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
689 event:0X0543 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP84 : (Group 84 pm_cpi_stack1) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of  PM_CMPLU_STALL_REJECT.
690 event:0X0544 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP84 : (Group 84 pm_cpi_stack1) Number of run instructions completed.
694 event:0X0550 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP85 : (Group 85 pm_cpi_stack2) FXU0 and FXU1 are both idle.
695 event:0X0551 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP85 : (Group 85 pm_cpi_stack2) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.
696 event:0X0552 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP85 : (Group 85 pm_cpi_stack2) A group completed. Microcoded instructions that span multiple groups will generate this event once per group.
697 event:0X0553 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP85 : (Group 85 pm_cpi_stack2) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.
698 event:0X0554 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP85 : (Group 85 pm_cpi_stack2) Number of run instructions completed.
702 event:0X0560 counters:0 um:zero minimum:1000 name:PM_TABLEWALK_CYC_GRP86 : (Group 86 pm_cpi_stack3) Cycles doing instruction or data tablewalks
703 event:0X0561 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP86 : (Group 86 pm_cpi_stack3) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.
704 event:0X0562 counters:2 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP86 : (Group 86 pm_cpi_stack3) Cycles a translation tablewalk is active.  While a tablewalk is active any request attempting to access the TLB will be rejected and retried.
705 event:0X0563 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP86 : (Group 86 pm_cpi_stack3) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.
706 event:0X0564 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP86 : (Group 86 pm_cpi_stack3) Number of run instructions completed.
710 event:0X0570 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP87 : (Group 87 pm_cpi_stack4) A floating point operation has completed
711 event:0X0571 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_SCALAR_LONG_GRP87 : (Group 87 pm_cpi_stack4) Completion stall caused by long latency scalar instruction
712 event:0X0572 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_GRP87 : (Group 87 pm_cpi_stack4) Marked Group Completion Stall cycles
713 event:0X0573 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_SCALAR_GRP87 : (Group 87 pm_cpi_stack4) Completion stall caused by FPU instruction
714 event:0X0574 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP87 : (Group 87 pm_cpi_stack4) Number of run instructions completed.
718 event:0X0580 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_END_GCT_NOSLOT_GRP88 : (Group 88 pm_cpi_stack5) Count ended because GCT went empty
719 event:0X0581 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_VECTOR_GRP88 : (Group 88 pm_cpi_stack5) Completion stall caused by Vector instruction
720 event:0X0582 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_COUNT_GRP88 : (Group 88 pm_cpi_stack5) Marked Group Completion Stall cycles (use edge detect to count #)
721 event:0X0583 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_GRP88 : (Group 88 pm_cpi_stack5) No groups completed, GCT not empty
722 event:0X0584 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP88 : (Group 88 pm_cpi_stack5) Number of run instructions completed.
726 event:0X0590 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_THRD_GRP89 : (Group 89 pm_cpi_stack6) Completion Stalled due to thread conflict.  Group ready to complete but it was another thread's turn
727 event:0X0591 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DFU_GRP89 : (Group 89 pm_cpi_stack6) Completion stall caused by Decimal Floating Point Unit
729 event:0X0593 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP89 : (Group 89 pm_cpi_stack6) No slot in GCT caused by branch mispredict or I cache miss
730 event:0X0594 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP89 : (Group 89 pm_cpi_stack6) Number of run instructions completed.
734 event:0X05A0 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread.
735 event:0X05A1 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.
736 event:0X05A2 counters:2 um:zero minimum:1000 name:PM_IOPS_DISP_GRP90 : (Group 90 pm_cpi_stack7) IOPS dispatched
737 event:0X05A3 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.
738 event:0X05A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP90 : (Group 90 pm_cpi_stack7) Number of run instructions completed.
742 event:0X05B0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP91 : (Group 91 pm_dsource1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
743 event:0X05B1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP91 : (Group 91 pm_dsource1) The processor's Data Cache was reloaded from the local L3 due to a demand load.
744 event:0X05B2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP91 : (Group 91 pm_dsource1) The processor?s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
745 event:0X05B3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP91 : (Group 91 pm_dsource1) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
746 event:0X05B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP91 : (Group 91 pm_dsource1) Number of run instructions completed.
750 event:0X05C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP92 : (Group 92 pm_dsource2) The processor's Data Cache was reloaded from the local L3 due to a demand load.
751 event:0X05C1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L31_SHR_GRP92 : (Group 92 pm_dsource2) Data loaded from another L3 on same chip shared
752 event:0X05C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP92 : (Group 92 pm_dsource2) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
753 event:0X05C3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP92 : (Group 92 pm_dsource2) The processor's Data Cache was reloaded but not from the local L2.
754 event:0X05C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP92 : (Group 92 pm_dsource2) Number of run instructions completed.
758 event:0X05D0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
759 event:0X05D1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded from beyond L3 due to a demand load
760 event:0X05D2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L21_MOD_GRP93 : (Group 93 pm_dsource3) Data loaded from another L2 on same chip modified
761 event:0X05D3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded but not from the local L2.
762 event:0X05D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP93 : (Group 93 pm_dsource3) Number of run instructions completed.
766 event:0X05E0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L31_MOD_GRP94 : (Group 94 pm_dsource4) Data loaded from another L3 on same chip modified
767 1000 name:PM_DATA_FROM_RL2L3_SHR_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
768 event:0X05E2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
769 event:0X05E3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
770 event:0X05E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP94 : (Group 94 pm_dsource4) Number of run instructions completed.
774 event:0X05F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L31_SHR_GRP95 : (Group 95 pm_dsource5) Data loaded from another L3 on same chip shared
775 event:0X05F1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP95 : (Group 95 pm_dsource5) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
776 event:0X05F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP95 : (Group 95 pm_dsource5) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
777 event:0X05F3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L21_SHR_GRP95 : (Group 95 pm_dsource5) Data loaded from another L2 on same chip shared
778 event:0X05F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP95 : (Group 95 pm_dsource5) Number of run instructions completed.
782 event:0X0600 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load
783 event:0X0601 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
784 event:0X0602 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L21_SHR_GRP96 : (Group 96 pm_dsource6) Data loaded from another L2 on same chip shared
785 event:0X0603 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded but not from the local L2.
786 event:0X0604 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP96 : (Group 96 pm_dsource6) Number of run instructions completed.
790 event:0X0610 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
791 event:0X0611 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded from beyond L3 due to a demand load
792 event:0X0612 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
793 event:0X0613 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
794 event:0X0614 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP97 : (Group 97 pm_dsource7) Number of run instructions completed.
799 event:0X0621 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP98 : (Group 98 pm_dsource8) The processor's Data Cache was reloaded from the local L3 due to a demand load.
800 event:0X0622 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP98 : (Group 98 pm_dsource8) The processor's Data Cache was reloaded from beyond L3 due to a demand load
801 event:0X0623 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP98 : (Group 98 pm_dsource8) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
802 event:0X0624 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP98 : (Group 98 pm_dsource8) Number of run instructions completed.
806 event:0X0630 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP99 : (Group 99 pm_dsource9) The processor's Data Cache was reloaded from the local L2 due to a demand load.
807 event:0X0631 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP99 : (Group 99 pm_dsource9) The processor's Data Cache was reloaded but not from the local L2.
808 event:0X0632 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP99 : (Group 99 pm_dsource9) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
809 event:0X0633 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP99 : (Group 99 pm_dsource9) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
810 event:0X0634 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP99 : (Group 99 pm_dsource9) Number of run instructions completed.
814 event:0X0640 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load
815 event:0X0641 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
816 event:0X0642 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
817 event:0X0643 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
818 event:0X0644 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP100 : (Group 100 pm_dsource10) Number of run instructions completed.
822 event:0X0650 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded from the local L2 due to a demand load.
823 event:0X0651 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded but not from the local L2.
824 event:0X0652 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded from beyond L3 due to a demand load
825 event:0X0653 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP101 : (Group 101 pm_dsource11) Number of run instructions completed.
826 event:0X0654 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP101 : (Group 101 pm_dsource11) Number of run instructions completed.
830 event:0X0660 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP102 : (Group 102 pm_dsource12) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a demand load
831 event:0X0661 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP102 : (Group 102 pm_dsource12) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
832 event:0X0662 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP102 : (Group 102 pm_dsource12) The processor?s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
833 event:0X0663 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP102 : (Group 102 pm_dsource12) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
834 event:0X0664 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP102 : (Group 102 pm_dsource12) Number of run instructions completed.
838 event:0X0670 counters:0 um:zero minimum:1000 name:PM_DERAT_MISS_4K_GRP103 : (Group 103 pm_dsource13) A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
840 event:0X0672 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP103 : (Group 103 pm_dsource13) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
841 event:0X0673 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP103 : (Group 103 pm_dsource13) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a demand load
842 event:0X0674 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP103 : (Group 103 pm_dsource13) Number of run instructions completed.
846 event:0X0680 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP104 : (Group 104 pm_dsource14) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
848 event:0X0682 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP104 : (Group 104 pm_dsource14) The processor?s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
849 event:0X0683 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP104 : (Group 104 pm_dsource14) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
850 event:0X0684 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP104 : (Group 104 pm_dsource14) Number of run instructions completed.
854 event:0X0690 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP105 : (Group 105 pm_dsource15) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
856 event:0X0692 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP105 : (Group 105 pm_dsource15) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
857 event:0X0693 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP105 : (Group 105 pm_dsource15) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
858 event:0X0694 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP105 : (Group 105 pm_dsource15) Number of run instructions completed.
862 event:0X06A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions
863 event:0X06A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
864 event:0X06A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
865 event:0X06A3 counters:3 um:zero minimum:1000
866 event:0X06A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP106 : (Group 106 pm_isource1) Number of run instructions completed.
870 event:0X06B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
871 event:0X06B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
872 event:0X06B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
873 event:0X06B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
874 event:0X06B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP107 : (Group 107 pm_isource2) Number of run instructions completed.
878 event:0X06C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
879 event:0X06C1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
880 event:0X06C2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
881 event:0X06C3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
882 event:0X06C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP108 : (Group 108 pm_isource3) Number of run instructions completed.
886 event:0X06D0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L31_MOD_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L3 on same chip modified
887 event:0X06D1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L31_SHR_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L3 on same chip shared
888 event:0X06D2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L21_MOD_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L2 on same chip modified
889 event:0X06D3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L21_SHR_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L2 on same chip shared
890 event:0X06D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP109 : (Group 109 pm_isource4) Number of run instructions completed.
894 event:0X06E0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L31_SHR_GRP110 : (Group 110 pm_isource5) Instruction fetched from another L3 on same chip shared
895 event:0X06E1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP110 : (Group 110 pm_isource5) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
896 event:0X06E2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L21_SHR_GRP110 : (Group 110 pm_isource5) Instruction fetched from another L2 on same chip shared
897 event:0X06E3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP110 : (Group 110 pm_isource5) An instruction fetch group was fetched from beyond the local L2.
898 event:0X06E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP110 : (Group 110 pm_isource5) Number of run instructions completed.
902 event:0X06F0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions
903 event:0X06F1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
904 event:0X06F2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
905 event:0X06F3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from beyond the local L2.
906 event:0X06F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP111 : (Group 111 pm_isource6) Number of run instructions completed.
910 event:0X0700 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_MOD_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
911 event:0X0701 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
912 event:0X0702 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
913 event:0X0703 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
914 event:0X0704 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP112 : (Group 112 pm_isource7) Number of run instructions completed.
918 event:0X0710 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
919 event:0X0711 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
920 event:0X0712 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
921 event:0X0713 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from beyond the local L2.
922 event:0X0714 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP113 : (Group 113 pm_isource8) Number of run instructions completed.
926 event:0X0720 counters:0 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions
927 event:0X0721 counters:1 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
928 event:0X0722 counters:2 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on.  Fetch groups can contain up to 8 instructions
929 event:0X0723 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
930 event:0X0724 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP114 : (Group 114 pm_isource9) Number of run instructions completed.
934 event:0X0730 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP115 : (Group 115 pm_isource10) An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions
935 event:0X0731 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP115 : (Group 115 pm_isource10) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
938 event:0X0734 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP115 : (Group 115 pm_isource10) Number of run instructions completed.
942 event:0X0740 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_MOD_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
943 event:0X0741 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
944 event:0X0742 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on.  Fetch groups can contain up to 8 instructions
946 event:0X0744 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP116 : (Group 116 pm_isource11) Number of run instructions completed.
952 event:0X0752 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP117 : (Group 117 pm_isource12) An instruction fetch group was fetched with shared  (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
953 event:0X0753 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP117 : (Group 117 pm_isource12) An instruction fetch group was fetched with modified  (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
954 event:0X0754 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP117 : (Group 117 pm_isource12) Number of run instructions completed.
958 event:0X0760 counters:0 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP118 : (Group 118 pm_isource13) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
960 event:0X0762 counters:2 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP118 : (Group 118 pm_isource13) An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on.  Fetch groups can contain up to 8 instructions
961 event:0X0763 counters:3 um:zero minimum:1000
962 event:0X0764 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP118 : (Group 118 pm_isource13) Number of run instructions completed.
966 event:0X0770 counters:0 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP119 : (Group 119 pm_prefetch1) D cache new prefetch stream allocated
967 event:0X0771 counters:1 um:zero minimum:1000 name:PM_L3_PREF_LDST_GRP119 : (Group 119 pm_prefetch1) L3 cache prefetches LD + ST
968 event:0X0772 counters:2 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_CONFIRM_GRP119 : (Group 119 pm_prefetch1) Dcache new prefetch stream confirmed
969 event:0X0773 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP119 : (Group 119 pm_prefetch1) A request to prefetch data into the L1 was made
970 event:0X0774 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP119 : (Group 119 pm_prefetch1) Number of run instructions completed.
974 event:0X0780 counters:0 um:zero minimum:1000 name:PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP120 : (Group 120 pm_prefetch2) Dcache Strided prefetch stream confirmed (software + hardware)
975 event:0X0781 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP120 : (Group 120 pm_prefetch2)  L1 D cache load references counted at finish
976 event:0X0782 counters:2 um:zero minimum:1000 name:PM_LSU_FIN_GRP120 : (Group 120 pm_prefetch2) LSU Finished an instruction (up to 2 per cycle)
977 event:0X0783 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP120 : (Group 120 pm_prefetch2) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
978 event:0X0784 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP120 : (Group 120 pm_prefetch2) Number of run instructions completed.
982 event:0X0790 counters:0 um:zero minimum:1000 name:PM_VSU0_1FLOP_GRP121 : (Group 121 pm_vsu0) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished
983 event:0X0791 counters:1 um:zero minimum:1000 name:PM_VSU1_1FLOP_GRP121 : (Group 121 pm_vsu0) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished
984 event:0X0792 counters:2 um:zero minimum:1000 name:PM_VSU0_2FLOP_GRP121 : (Group 121 pm_vsu0) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
985 event:0X0793 counters:3 um:zero minimum:1000 name:PM_VSU1_2FLOP_GRP121 : (Group 121 pm_vsu0) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
986 event:0X0794 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP121 : (Group 121 pm_vsu0) Number of run instructions completed.
990 event:0X07A0 counters:0 um:zero minimum:1000 name:PM_VSU0_4FLOP_GRP122 : (Group 122 pm_vsu1) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
991 event:0X07A1 counters:1 um:zero minimum:1000 name:PM_VSU1_4FLOP_GRP122 : (Group 122 pm_vsu1) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
992 event:0X07A2 counters:2 um:zero minimum:1000 name:PM_VSU0_8FLOP_GRP122 : (Group 122 pm_vsu1) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
993 event:0X07A3 counters:3 um:zero minimum:1000 name:PM_VSU1_8FLOP_GRP122 : (Group 122 pm_vsu1) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
994 event:0X07A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP122 : (Group 122 pm_vsu1) Number of run instructions completed.
998 event:0X07B0 counters:0 um:zero minimum:1000 name:PM_VSU_2FLOP_GRP123 : (Group 123 pm_vsu2) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
999 event:0X07B1 counters:1 um:zero minimum:1000 name:PM_VSU_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg
1000 event:0X07B2 counters:2 um:zero minimum:1000 name:PM_VSU0_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)
1001 event:0X07B3 counters:3 um:zero minimum:1000 name:PM_VSU1_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)
1002 event:0X07B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP123 : (Group 123 pm_vsu2) Number of run instructions completed.
1006 event:0X07C0 counters:0 um:zero minimum:1000 name:PM_VSU0_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!
1007 event:0X07C1 counters:1 um:zero minimum:1000 name:PM_VSU1_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!
1008 event:0X07C2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
1010 event:0X07C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP124 : (Group 124 pm_vsu3) Number of run instructions completed.
1014 event:0X07D0 counters:0 um:zero minimum:1000 name:PM_VSU0_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)
1015 event:0X07D1 counters:1 um:zero minimum:1000 name:PM_VSU1_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)
1016 event:0X07D2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) DP vector version of fmadd,fnmadd,fmsub,fnmsub
1018 event:0X07D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP125 : (Group 125 pm_vsu4) Number of run instructions completed.
1022 event:0X07E0 counters:0 um:zero minimum:1000 name:PM_VSU_VECTOR_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe0
1023 event:0X07E1 counters:1 um:zero minimum:1000 name:PM_VSU0_VECT_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe0
1024 event:0X07E2 counters:2 um:zero minimum:1000 name:PM_VSU1_VECT_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe1
1026 event:0X07E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP126 : (Group 126 pm_vsu5) Number of run instructions completed.
1030 event:0X07F0 counters:0 um:zero minimum:1000 name:PM_VSU_DENORM_GRP127 : (Group 127 pm_vsu6) Vector or Scalar denorm operand
1031 event:0X07F1 counters:1 um:zero minimum:1000 name:PM_VSU0_DENORM_GRP127 : (Group 127 pm_vsu6) VSU0 received denormalized data
1032 event:0X07F2 counters:2 um:zero minimum:1000 name:PM_VSU1_DENORM_GRP127 : (Group 127 pm_vsu6) VSU1 received denormalized data
1034 event:0X07F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP127 : (Group 127 pm_vsu6) Number of run instructions completed.
1038 event:0X0800 counters:0 um:zero minimum:1000 name:PM_VSU_FIN_GRP128 : (Group 128 pm_vsu7) VSU0 Finished an instruction
1039 event:0X0801 counters:1 um:zero minimum:1000 name:PM_VSU0_FIN_GRP128 : (Group 128 pm_vsu7) VSU0 Finished an instruction
1040 event:0X0802 counters:2 um:zero minimum:1000 name:PM_VSU1_FIN_GRP128 : (Group 128 pm_vsu7) VSU1 Finished an instruction
1042 event:0X0804 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP128 : (Group 128 pm_vsu7) Number of run instructions completed.
1046 event:0X0810 counters:0 um:zero minimum:1000 name:PM_VSU_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe0
1047 event:0X0811 counters:1 um:zero minimum:1000 name:PM_VSU0_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe0
1048 event:0X0812 counters:2 um:zero minimum:1000 name:PM_VSU1_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe1
1050 event:0X0814 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP129 : (Group 129 pm_vsu8) Number of run instructions completed.
1054 event:0X0820 counters:0 um:zero minimum:1000 name:PM_VSU_SINGLE_GRP130 : (Group 130 pm_vsu9) Vector or Scalar single precision
1055 event:0X0821 counters:1 um:zero minimum:1000 name:PM_VSU0_SINGLE_GRP130 : (Group 130 pm_vsu9) VSU0 executed single precision instruction
1056 event:0X0822 counters:2 um:zero minimum:1000 name:PM_VSU1_SINGLE_GRP130 : (Group 130 pm_vsu9) VSU1 executed single precision instruction
1057 event:0X0823 counters:3 um:zero minimum:1000 name:PM_VSU0_16FLOP_GRP130 : (Group 130 pm_vsu9) Sixteen flops operation (SP vector versions of fdiv,fsqrt)
1058 event:0X0824 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP130 : (Group 130 pm_vsu9) Number of run instructions completed.
1062 event:0X0830 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) DP vector versions of fdiv,fsqrt
1063 event:0X0831 counters:1 um:zero minimum:1000 name:PM_VSU0_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!
1064 event:0X0832 counters:2 um:zero minimum:1000 name:PM_VSU1_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!
1066 event:0X0834 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP131 : (Group 131 pm_vsu10) Number of run instructions completed.
1070 event:0X0840 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) DP vector versions of fdiv,fsqrt
1071 event:0X0841 counters:1 um:zero minimum:1000 name:PM_VSU0_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) eight flop DP vector operations (xvfdivdp, xvsqrtdp
1072 event:0X0842 counters:2 um:zero minimum:1000 name:PM_VSU1_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) eight flop DP vector operations (xvfdivdp, xvsqrtdp
1074 event:0X0844 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP132 : (Group 132 pm_vsu11) Number of run instructions completed.
1078 event:0X0850 counters:0 um:zero minimum:1000 name:PM_VSU_SCALAR_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe0
1079 event:0X0851 counters:1 um:zero minimum:1000 name:PM_VSU0_SCAL_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe0
1080 event:0X0852 counters:2 um:zero minimum:1000 name:PM_VSU1_SCAL_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe1
1082 event:0X0854 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP133 : (Group 133 pm_vsu12) Number of run instructions completed.
1086 event:0X0860 counters:0 um:zero minimum:1000 name:PM_VSU_SCALAR_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe0
1087 event:0X0861 counters:1 um:zero minimum:1000 name:PM_VSU0_SCAL_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe0
1088 event:0X0862 counters:2 um:zero minimum:1000 name:PM_VSU1_SCAL_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe1
1090 event:0X0864 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP134 : (Group 134 pm_vsu13) Number of run instructions completed.
1094 event:0X0870 counters:0 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP135 : (Group 135 pm_vsu14) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
1095 event:0X0871 counters:1 um:zero minimum:1000 name:PM_VSU_4FLOP_GRP135 : (Group 135 pm_vsu14) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
1096 event:0X0872 counters:2 um:zero minimum:1000 name:PM_VSU_8FLOP_GRP135 : (Group 135 pm_vsu14) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
1097 event:0X0873 counters:3 um:zero minimum:1000 name:PM_VSU_2FLOP_GRP135 : (Group 135 pm_vsu14) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
1098 event:0X0874 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP135 : (Group 135 pm_vsu14) Number of run instructions completed.
1102 event:0X0880 counters:0 um:zero minimum:1000 name:PM_VSU_VECTOR_SINGLE_ISSUED_GRP136 : (Group 136 pm_vsu15) Single Precision vector instruction issued (executed)
1103 event:0X0881 counters:1 um:zero minimum:1000 name:PM_VSU0_VECTOR_SP_ISSUED_GRP136 : (Group 136 pm_vsu15) Single Precision vector instruction issued (executed)
1104 event:0X0882 counters:2 um:zero minimum:1000 name:PM_VSU0_FPSCR_GRP136 : (Group 136 pm_vsu15) Move to/from FPSCR type instruction issued on Pipe 0
1106 event:0X0884 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP136 : (Group 136 pm_vsu15) Number of run instructions completed.
1110 event:0X0890 counters:0 um:zero minimum:1000 name:PM_VSU_SIMPLE_ISSUED_GRP137 : (Group 137 pm_vsu16) Simple VMX instruction issued
1111 event:0X0891 counters:1 um:zero minimum:1000 name:PM_VSU0_SIMPLE_ISSUED_GRP137 : (Group 137 pm_vsu16) Simple VMX instruction issued
1112 event:0X0892 counters:2 um:zero minimum:1000 name:PM_VSU0_COMPLEX_ISSUED_GRP137 : (Group 137 pm_vsu16) Complex VMX instruction issued
1113 event:0X0893 counters:3 um:zero minimum:1000 name:PM_VMX_RESULT_SAT_1_GRP137 : (Group 137 pm_vsu16) Valid result with sat=1
1114 event:0X0894 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP137 : (Group 137 pm_vsu16) Number of run instructions completed.
1118 event:0X08A0 counters:0 um:zero minimum:1000 name:PM_VSU1_DD_ISSUED_GRP138 : (Group 138 pm_vsu17) 64BIT Decimal Issued on Pipe1
1119 event:0X08A1 counters:1 um:zero minimum:1000 name:PM_VSU1_DQ_ISSUED_GRP138 : (Group 138 pm_vsu17) 128BIT Decimal Issued on Pipe1
1120 event:0X08A2 counters:2 um:zero minimum:1000 name:PM_VSU1_PERMUTE_ISSUED_GRP138 : (Group 138 pm_vsu17) Permute VMX Instruction Issued
1121 event:0X08A3 counters:3 um:zero minimum:1000 name:PM_VSU1_SQ_GRP138 : (Group 138 pm_vsu17) Store Vector Issued on Pipe1
1122 event:0X08A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP138 : (Group 138 pm_vsu17) Number of run instructions completed.
1126 event:0X08B0 counters:0 um:zero minimum:1000 name:PM_VSU_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
1127 event:0X08B1 counters:1 um:zero minimum:1000 name:PM_VSU0_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
1128 event:0X08B2 counters:2 um:zero minimum:1000 name:PM_VSU1_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
1130 event:0X08B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP139 : (Group 139 pm_vsu18) Number of run instructions completed.
1134 event:0X08C0 counters:0 um:zero minimum:1000 name:PM_VSU_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
1135 event:0X08C1 counters:1 um:zero minimum:1000 name:PM_VSU0_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
1136 event:0X08C2 counters:2 um:zero minimum:1000 name:PM_VSU1_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
1138 event:0X08C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP140 : (Group 140 pm_vsu19) Number of run instructions completed.
1142 event:0X08D0 counters:0 um:zero minimum:1000 name:PM_VSU_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
1143 event:0X08D1 counters:1 um:zero minimum:1000 name:PM_VSU0_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
1144 event:0X08D2 counters:2 um:zero minimum:1000 name:PM_VSU1_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
1146 event:0X08D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP141 : (Group 141 pm_vsu20) Number of run instructions completed.
1150 event:0X08E0 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP142 : (Group 142 pm_vsu21) The Branch execution unit finished an instruction
1153 event:0X08E3 counters:3 um:zero minimum:1000 name:PM_VSU_FIN_GRP142 : (Group 142 pm_vsu21) VSU0 Finished an instruction
1154 event:0X08E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP142 : (Group 142 pm_vsu21) Number of run instructions completed.
1158 event:0X08F0 counters:0 um:zero minimum:1000 name:PM_LSU_LDF_GRP143 : (Group 143 pm_vsu22) LSU executed Floating Point load instruction.  Combined Unit 0 + 1.
1159 event:0X08F1 counters:1 um:zero minimum:1000 name:PM_VSU_STF_GRP143 : (Group 143 pm_vsu22) FPU store (SP or DP) issued on Pipe0
1160 event:0X08F2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP143 : (Group 143 pm_vsu22) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
1161 event:0X08F3 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP143 : (Group 143 pm_vsu22) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
1162 event:0X08F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP143 : (Group 143 pm_vsu22) Number of run instructions completed.
1166 event:0X0900 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_GRP144 : (Group 144 pm_vsu23) DP vector versions of fdiv,fsqrt
1167 event:0X0901 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP144 : (Group 144 pm_vsu23) VSU0 Finished an instruction
1168 event:0X0902 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP144 : (Group 144 pm_vsu23) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
1169 event:0X0903 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP144 : (Group 144 pm_vsu23) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
1170 event:0X0904 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP144 : (Group 144 pm_vsu23) Number of run instructions completed.
1174 event:0X0910 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP145 : (Group 145 pm_vsu24) A floating point operation has completed
1175 event:0X0911 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP145 : (Group 145 pm_vsu24) VSU0 Finished an instruction
1176 event:0X0912 counters:2 um:zero minimum:1000 name:PM_VSU_FEST_GRP145 : (Group 145 pm_vsu24) Estimate instruction executed
1177 event:0X0913 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP145 : (Group 145 pm_vsu24) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
1178 event:0X0914 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP145 : (Group 145 pm_vsu24) Number of run instructions completed.
1182 event:0X0920 counters:0 um:zero minimum:1000 name:PM_VSU_STF_GRP146 : (Group 146 pm_vsu25) FPU store (SP or DP) issued on Pipe0
1183 event:0X0921 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP146 : (Group 146 pm_vsu25) VSU0 Finished an instruction
1184 event:0X0922 counters:2 um:zero minimum:1000 name:PM_VSU_FRSP_GRP146 : (Group 146 pm_vsu25) Round to single precision instruction executed
1185 event:0X0923 counters:3 um:zero minimum:1000 name:PM_VSU_FCONV_GRP146 : (Group 146 pm_vsu25) Convert instruction executed
1186 event:0X0924 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP146 : (Group 146 pm_vsu25) Number of run instructions completed.
1190 event:0X0930 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP147 : (Group 147 pm_lsu1) The Load Miss Queue was full.
1191 event:0X0931 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP147 : (Group 147 pm_lsu1) Cycles when both the LMQ and SRQ are empty (LSU is idle)
1192 event:0X0932 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC_GRP147 : (Group 147 pm_lsu1) ALL threads lsu empty (lmq and srq empty)
1193 event:0X0933 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP147 : (Group 147 pm_lsu1) The Store Request Queue is empty
1194 event:0X0934 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP147 : (Group 147 pm_lsu1) Number of run instructions completed.
1198 event:0X0940 counters:0 um:zero minimum:1000 name:PM_LSU_FX_FIN_GRP148 : (Group 148 pm_lsu2) LSU Finished a FX operation  (up to 2 per cycle)
1199 event:0X0941 counters:1 um:zero minimum:1000 name:PM_LSU_NCST_GRP148 : (Group 148 pm_lsu2) Non-cachable Stores sent to nest
1200 event:0X0942 counters:2 um:zero minimum:1000 name:PM_LSU_FIN_GRP148 : (Group 148 pm_lsu2) LSU Finished an instruction (up to 2 per cycle)
1201 event:0X0943 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP148 : (Group 148 pm_lsu2) A flush was initiated by the Load Store Unit.
1202 event:0X0944 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP148 : (Group 148 pm_lsu2) Number of run instructions completed.
1206 event:0X0950 counters:0 um:zero minimum:1000 name:PM_LSU0_LMQ_LHR_MERGE_GRP149 : (Group 149 pm_lsu_lmq) LS0  Load Merged with another cacheline request
1207 event:0X0951 counters:1 um:zero minimum:1000 name:PM_LSU1_LMQ_LHR_MERGE_GRP149 : (Group 149 pm_lsu_lmq) LS1 Load Merge with another cacheline request
1208 event:0X0952 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP149 : (Group 149 pm_lsu_lmq) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the LRQ is split between the two threads (16 entries each).
1209 event:0X0953 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP149 : (Group 149 pm_lsu_lmq) The Load Miss Queue was full.
1210 event:0X0954 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP149 : (Group 149 pm_lsu_lmq) Number of run instructions completed.
1214 event:0X0960 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.
1215 event:0X0961 counters:1 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load on unit 0.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.
1216 event:0X0962 counters:2 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load on unit 1.  A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted.  It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.
1218 event:0X0964 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP150 : (Group 150 pm_lsu_srq1) Number of run instructions completed.
1222 event:0X0970 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP151 : (Group 151 pm_lsu_srq2) Cycles that a sync instruction is active in the Store Request Queue.
1223 event:0X0971 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_COUNT_GRP151 : (Group 151 pm_lsu_srq2) SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)
1224 event:0X0972 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP151 : (Group 151 pm_lsu_srq2) This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the SRQ is split between the two threads (16 entries each).
1226 event:0X0974 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP151 : (Group 151 pm_lsu_srq2) Number of run instructions completed.
1230 event:0X0980 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the SRQ is split between the two threads (16 entries each).
1231 event:0X0981 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the LRQ is split between the two threads (16 entries each).
1232 event:0X0982 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.  In SMT mode the LRQ is split between the two threads (16 entries each).
1234 event:0X0984 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP152 : (Group 152 pm_lsu_s0_valid) Number of run instructions completed.
1238 event:0X0990 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of LMQ valid
1239 event:0X0991 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of LRQ valid
1240 event:0X0992 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of SRQ valid
1242 event:0X0994 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP153 : (Group 153 pm_lsu_s0_alloc) Number of run instructions completed.
1246 event:0X09A0 counters:0 um:zero minimum:1000 name:PM_L1_PREF_GRP154 : (Group 154 pm_l1_pref) A request to prefetch data into the L1 was made
1247 event:0X09A1 counters:1 um:zero minimum:1000 name:PM_LSU0_L1_PREF_GRP154 : (Group 154 pm_l1_pref)  LS0 L1 cache data prefetches
1248 event:0X09A2 counters:2 um:zero minimum:1000 name:PM_LSU1_L1_PREF_GRP154 : (Group 154 pm_l1_pref)  LS1 L1 cache data prefetches
1250 event:0X09A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP154 : (Group 154 pm_l1_pref) Number of run instructions completed.
1254 event:0X09B0 counters:0 um:zero minimum:1000 name:PM_L2_LOC_GUESS_CORRECT_GRP155 : (Group 155 pm_l2_guess_1) L2 guess loc and guess was correct (ie data local)
1255 event:0X09B1 counters:1 um:zero minimum:1000 name:PM_L2_LOC_GUESS_WRONG_GRP155 : (Group 155 pm_l2_guess_1) L2 guess loc and guess was not correct (ie data remote)
1258 event:0X09B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP155 : (Group 155 pm_l2_guess_1) Number of run instructions completed.
1262 event:0X09C0 counters:0 um:zero minimum:1000 name:PM_L2_GLOB_GUESS_CORRECT_GRP156 : (Group 156 pm_l2_guess_2) L2 guess glb and guess was correct (ie data remote)
1263 event:0X09C1 counters:1 um:zero minimum:1000 name:PM_L2_GLOB_GUESS_WRONG_GRP156 : (Group 156 pm_l2_guess_2) L2 guess glb and guess was not correct (ie data local)
1266 event:0X09C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP156 : (Group 156 pm_l2_guess_2) Number of run instructions completed.
1270 event:0X09D0 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP157 : (Group 157 pm_misc1) Number of instructions resulting from the marked instructions expansion that completed.
1271 event:0X09D1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP157 : (Group 157 pm_misc1) An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
1272 event:0X09D2 counters:2 um:zero minimum:1000 name:PM_INST_IMC_MATCH_DISP_GRP157 : (Group 157 pm_misc1) IMC Matches dispatched
1274 event:0X09D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP157 : (Group 157 pm_misc1) Number of run instructions completed.
1278 event:0X09E0 counters:0 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP158 : (Group 158 pm_misc2) Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
1279 event:0X09E1 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP158 : (Group 158 pm_misc2) An interrupt due to an external exception occurred
1280 event:0X09E2 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP158 : (Group 158 pm_misc2) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
1282 event:0X09E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP158 : (Group 158 pm_misc2) Number of run instructions completed.
1286 event:0X09F0 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP159 : (Group 159 pm_misc3) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
1287 event:0X09F1 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP159 : (Group 159 pm_misc3) Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
1288 event:0X09F2 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP159 : (Group 159 pm_misc3) Number of PowerPC instructions successfully dispatched.
1289 event:0X09F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP159 : (Group 159 pm_misc3) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
1290 event:0X09F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP159 : (Group 159 pm_misc3) Number of run instructions completed.
1294 event:0X0A00 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP160 : (Group 160 pm_misc4) Number of groups, counted at completion, that have encountered an instruction cache miss.
1295 event:0X0A01 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP160 : (Group 160 pm_misc4) Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.
1297 event:0X0A03 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP160 : (Group 160 pm_misc4) No slot in GCT caused by branch mispredict or I cache miss
1298 event:0X0A04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP160 : (Group 160 pm_misc4) Number of run instructions completed.
1302 1000 name:PM_GRP_BR_MPRED_NONSPEC_GRP161 : (Group 161 pm_misc5) Group experienced non-speculative branch redirect
1303 event:0X0A11 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_TA_GRP161 : (Group 161 pm_misc5) Branch mispredict - taken/not taken and target
1304 event:0X0A12 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP161 : (Group 161 pm_misc5) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
1305 event:0X0A13 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP161 : (Group 161 pm_misc5) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
1306 event:0X0A14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP161 : (Group 161 pm_misc5) Number of run instructions completed.
1310 event:0X0A20 counters:0 um:zero minimum:1000 name:PM_L1_DEMAND_WRITE_GRP162 : (Group 162 pm_misc6) Instruction Demand sectors wriittent into IL1
1311 event:0X0A21 counters:1 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP162 : (Group 162 pm_misc6) Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
1312 event:0X0A22 counters:2 um:zero minimum:1000 name:PM_IC_WRITE_ALL_GRP162 : (Group 162 pm_misc6) Icache sectors written, prefetch + demand
1314 event:0X0A24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP162 : (Group 162 pm_misc6) Number of run instructions completed.
1318 event:0X0A30 counters:0 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP163 : (Group 163 pm_misc7) The threshold timer expired
1319 event:0X0A31 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP163 : (Group 163 pm_misc7) Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
1321 event:0X0A33 counters:3 um:zero minimum:1000 name:PM_IFU_FIN_GRP163 : (Group 163 pm_misc7) The Instruction Fetch Unit finished an instruction
1322 event:0X0A34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP163 : (Group 163 pm_misc7) Number of run instructions completed.
1326 event:0X0A40 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_LSTACK_GRP164 : (Group 164 pm_misc8) Branch Mispredict due to Link Stack
1327 event:0X0A41 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP164 : (Group 164 pm_misc8) An interrupt due to an external exception occurred
1328 event:0X0A42 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP164 : (Group 164 pm_misc8) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
1329 event:0X0A43 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP164 : (Group 164 pm_misc8) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
1330 event:0X0A44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP164 : (Group 164 pm_misc8) Number of run instructions completed.
1334 event:0X0A50 counters:0 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP165 : (Group 165 pm_misc9) A flush was caused by a branch mispredict.
1335 event:0X0A51 counters:1 um:zero minimum:1000 name:PM_FLUSH_PARTIAL_GRP165 : (Group 165 pm_misc9) Partial flush
1336 event:0X0A52 counters:2 um:zero minimum:1000 name:PM_LSU_SET_MPRED_GRP165 : (Group 165 pm_misc9) Line already in cache at reload time
1337 event:0X0A53 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP165 : (Group 165 pm_misc9) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
1338 event:0X0A54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP165 : (Group 165 pm_misc9) Number of run instructions completed.
1342 event:0X0A60 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP166 : (Group 166 pm_misc10) Cycles the Store Request Queue is full.
1343 event:0X0A61 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP166 : (Group 166 pm_misc10) D cache new prefetch stream allocated
1344 event:0X0A62 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP166 : (Group 166 pm_misc10) A request to prefetch data into the L1 was made
1345 event:0X0A63 counters:3 um:zero minimum:1000 name:PM_IBUF_FULL_CYC_GRP166 : (Group 166 pm_misc10) Cycles with the Instruction Buffer was full.  The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
1346 event:0X0A64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP166 : (Group 166 pm_misc10) Number of run instructions completed.
1350 event:0X0A70 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP167 : (Group 167 pm_misc11) A floating point operation has completed
1352 event:0X0A72 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP167 : (Group 167 pm_misc11) A group completed. Microcoded instructions that span multiple groups will generate this event once per group.
1354 event:0X0A74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP167 : (Group 167 pm_misc11) Number of run instructions completed.
1359 event:0X0A81 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP168 : (Group 168 pm_misc_12) Store requests sent to the nest.
1360 event:0X0A82 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP168 : (Group 168 pm_misc_12) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
1361 event:0X0A83 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP168 : (Group 168 pm_misc_12) Flushes occurred including LSU and Branch flushes.
1362 event:0X0A84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP168 : (Group 168 pm_misc_12) Number of run instructions completed.
1366 event:0X0A90 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP169 : (Group 169 pm_misc_13) Cycles when the Global Completion Table has no slots from this thread.
1367 event:0X0A91 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP169 : (Group 169 pm_misc_13) Store requests sent to the nest.
1368 event:0X0A92 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP169 : (Group 169 pm_misc_13) Data TLB misses, all page sizes.
1369 event:0X0A93 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP169 : (Group 169 pm_misc_13) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
1370 event:0X0A94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP169 : (Group 169 pm_misc_13) Number of run instructions completed.
1377 event:0X0AA3 counters:3 um:zero minimum:1000 name:PM_IFU_FIN_GRP170 : (Group 170 pm_misc_14) The Instruction Fetch Unit finished an instruction
1378 event:0X0AA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP170 : (Group 170 pm_misc_14) Number of run instructions completed.
1382 event:0X0AB0 counters:0 um:zero minimum:1000 name:PM_LSU_DCACHE_RELOAD_VALID_GRP171 : (Group 171 pm_misc_15) count per sector of lines reloaded in L1 (demand + prefetch)
1383 event:0X0AB1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_STORE_GRP171 : (Group 171 pm_misc_15) Completion stall due to store instruction
1384 event:0X0AB2 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP171 : (Group 171 pm_misc_15) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
1385 event:0X0AB3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_VECTOR_LONG_GRP171 : (Group 171 pm_misc_15) completion stall due to long latency vector instruction
1386 event:0X0AB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP171 : (Group 171 pm_misc_15) Number of run instructions completed.
1390 event:0X0AC0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_END_GCT_NOSLOT_GRP172 : (Group 172 pm_misc_16) Count ended because GCT went empty
1391 event:0X0AC1 counters:1 um:zero minimum:1000 name:PM_LSU0_L1_SW_PREF_GRP172 : (Group 172 pm_misc_16) LSU0 Software L1 Prefetches, including SW Transient Prefetches
1392 event:0X0AC2 counters:2 um:zero minimum:1000 name:PM_LSU1_L1_SW_PREF_GRP172 : (Group 172 pm_misc_16) LSU1 Software L1 Prefetches, including SW Transient Prefetches
1393 event:0X0AC3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_IFU_GRP172 : (Group 172 pm_misc_16) Completion stall due to IFU
1394 event:0X0AC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP172 : (Group 172 pm_misc_16) Number of run instructions completed.
1398 event:0X0AD0 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP173 : (Group 173 pm_misc_17) The Branch execution unit finished an instruction
1399 event:0X0AD1 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP173 : (Group 173 pm_misc_17) Store requests sent to the nest.
1400 event:0X0AD2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_SHR_GRP173 : (Group 173 pm_misc_17) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
1401 event:0X0AD3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_BRU_GRP173 : (Group 173 pm_misc_17) Completion stall due to BRU
1402 event:0X0AD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP173 : (Group 173 pm_misc_17) Number of run instructions completed.
1406 event:0X0AE0 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP174 : (Group 174 pm_suspend) The counter is suspended (does not count)
1408 event:0X0AE2 counters:2 um:zero minimum:1000 name:PM_LWSYNC_GRP174 : (Group 174 pm_suspend) lwsync count (easier to use than IMC)
1410 event:0X0AE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP174 : (Group 174 pm_suspend) Number of run instructions completed.
1414 event:0X0AF0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP175 : (Group 175 pm_iops) Number of internal operations that completed.
1416 event:0X0AF2 counters:2 um:zero minimum:1000 name:PM_IOPS_DISP_GRP175 : (Group 175 pm_iops) IOPS dispatched
1418 event:0X0AF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP175 : (Group 175 pm_iops) Number of run instructions completed.
1422 event:0X0B00 counters:0 um:zero minimum:1000 name:PM_LWSYNC_GRP176 : (Group 176 pm_sync) lwsync count (easier to use than IMC)
1424 event:0X0B02 counters:2 um:zero minimum:1000 name:PM_LWSYNC_HELD_GRP176 : (Group 176 pm_sync) Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.
1426 event:0X0B04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP176 : (Group 176 pm_sync) Number of run instructions completed.
1431 event:0X0B11 counters:1 um:zero minimum:1000 name:PM_SEG_EXCEPTION_GRP177 : (Group 177 pm_seg) ISEG + DSEG Exception
1432 event:0X0B12 counters:2 um:zero minimum:1000 name:PM_ISEG_GRP177 : (Group 177 pm_seg) ISEG Exception
1433 event:0X0B13 counters:3 um:zero minimum:1000 name:PM_DSEG_GRP177 : (Group 177 pm_seg) DSEG Exception
1434 event:0X0B14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP177 : (Group 177 pm_seg) Number of run instructions completed.
1438 event:0X0B20 counters:0 um:zero minimum:1000 name:PM_L3_HIT_GRP178 : (Group 178 pm_l3_hit) L3 Hits
1439 event:0X0B21 counters:1 um:zero minimum:1000 name:PM_L3_LD_HIT_GRP178 : (Group 178 pm_l3_hit) L3 demand LD Hits
1440 event:0X0B22 counters:2 um:zero minimum:1000 name:PM_L3_PREF_HIT_GRP178 : (Group 178 pm_l3_hit) L3 Prefetch Directory Hit
1441 event:0X0B23 counters:3 um:zero minimum:1000 name:PM_L3_CO_L31_GRP178 : (Group 178 pm_l3_hit) L3 Castouts to Memory
1442 event:0X0B24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP178 : (Group 178 pm_l3_hit) Number of run instructions completed.
1446 event:0X0B30 counters:0 um:zero minimum:1000 name:PM_SHL_DEALLOCATED_GRP179 : (Group 179 pm_shl) SHL Table entry deallocated
1447 event:0X0B31 counters:1 um:zero minimum:1000 name:PM_SHL_CREATED_GRP179 : (Group 179 pm_shl) SHL table entry Created
1448 event:0X0B32 counters:2 um:zero minimum:1000 name:PM_SHL_MERGED_GRP179 : (Group 179 pm_shl) SHL table entry merged with existing
1449 event:0X0B33 counters:3 um:zero minimum:1000 name:PM_SHL_MATCH_GRP179 : (Group 179 pm_shl) SHL Table Match
1450 event:0X0B34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP179 : (Group 179 pm_shl) Number of run instructions completed.
1454 event:0X0B40 counters:0 um:zero minimum:1000 name:PM_L3_PREF_LD_GRP180 : (Group 180 pm_l3_pref) L3 cache LD prefetches
1455 event:0X0B41 counters:1 um:zero minimum:1000 name:PM_L3_PREF_ST_GRP180 : (Group 180 pm_l3_pref) L3 cache ST prefetches
1456 event:0X0B42 counters:2 um:zero minimum:1000 name:PM_L3_PREF_LDST_GRP180 : (Group 180 pm_l3_pref) L3 cache prefetches LD + ST
1457 event:0X0B43 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP180 : (Group 180 pm_l3_pref) A request to prefetch data into the L1 was made
1458 event:0X0B44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP180 : (Group 180 pm_l3_pref) Number of run instructions completed.
1462 event:0X0B50 counters:0 um:zero minimum:1000 name:PM_L3_MISS_GRP181 : (Group 181 pm_l3) L3 Misses
1463 event:0X0B51 counters:1 um:zero minimum:1000 name:PM_L3_LD_MISS_GRP181 : (Group 181 pm_l3) L3 demand LD Miss
1464 event:0X0B52 counters:2 um:zero minimum:1000 name:PM_L3_PREF_MISS_GRP181 : (Group 181 pm_l3) L3 Prefetch  Directory Miss
1465 event:0X0B53 counters:3 um:zero minimum:1000 name:PM_L3_CO_MEM_GRP181 : (Group 181 pm_l3) L3 Castouts to L3.1
1466 event:0X0B54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP181 : (Group 181 pm_l3) Number of run instructions completed.
1471 event:0X0B61 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) Dcache new prefetch stream confirmed
1472 event:0X0B62 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) LS0 Dcache prefetch stream confirmed
1473 event:0X0B63 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) LS1 'Dcache prefetch stream confirmed
1474 event:0X0B64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP182 : (Group 182 pm_streams1) Number of run instructions completed.
1479 event:0X0B71 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP183 : (Group 183 pm_streams2) Dcache Strided prefetch stream confirmed (software + hardware)
1480 event:0X0B72 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE_GRP183 : (Group 183 pm_streams2) LS0 Dcache Strided prefetch stream confirmed
1481 event:0X0B73 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE_GRP183 : (Group 183 pm_streams2) LS1  Dcache Strided prefetch stream confirmed
1482 event:0X0B74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP183 : (Group 183 pm_streams2) Number of run instructions completed.
1486 event:0X0B80 counters:0 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP184 : (Group 184 pm_streams3) A prefetch stream was started using the DST instruction.
1487 event:0X0B81 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) D cache new prefetch stream allocated
1488 event:0X0B82 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) LS0 D cache new prefetch stream allocated
1489 event:0X0B83 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) LS 1 D cache new prefetch stream allocated
1490 event:0X0B84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP184 : (Group 184 pm_streams3) Number of run instructions completed.
1494 event:0X0B90 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP185 : (Group 185 pm_larx) A larx (lwarx or ldarx) was executed on side 0
1495 event:0X0B91 counters:1 um:zero minimum:1000 name:PM_LARX_LSU1_GRP185 : (Group 185 pm_larx) A larx (lwarx or ldarx) was executed on side 1
1497 event:0X0B93 counters:3 um:zero minimum:1000 name:PM_LARX_LSU_GRP185 : (Group 185 pm_larx) Larx Finished
1498 event:0X0B94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP185 : (Group 185 pm_larx) Number of run instructions completed.
1503 event:0X0BA1 counters:1 um:zero minimum:1000 name:PM_LSU_LDF_GRP186 : (Group 186 pm_ldf) LSU executed Floating Point load instruction.  Combined Unit 0 + 1.
1504 event:0X0BA2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP186 : (Group 186 pm_ldf) A floating point load was executed by LSU0
1505 event:0X0BA3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP186 : (Group 186 pm_ldf) A floating point load was executed by LSU1
1506 event:0X0BA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP186 : (Group 186 pm_ldf) Number of run instructions completed.
1511 event:0X0BB1 counters:1 um:zero minimum:1000 name:PM_LSU_LDX_GRP187 : (Group 187 pm_ldx) All Vector loads (vsx vector + vmx vector)
1512 event:0X0BB2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDX_GRP187 : (Group 187 pm_ldx) LS0 Vector Loads
1513 event:0X0BB3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDX_GRP187 : (Group 187 pm_ldx) LS1  Vector Loads
1514 event:0X0BB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP187 : (Group 187 pm_ldx) Number of run instructions completed.
1518 event:0X0BC0 counters:0 um:zero minimum:1000 name:PM_L2_LD_GRP188 : (Group 188 pm_l2_ld_st) Data Load Count
1519 event:0X0BC1 counters:1 um:zero minimum:1000 name:PM_L2_ST_MISS_GRP188 : (Group 188 pm_l2_ld_st) Data Store Miss
1520 event:0X0BC2 counters:2 um:zero minimum:1000 name:PM_L3_PREF_HIT_GRP188 : (Group 188 pm_l2_ld_st) L3 Prefetch Directory Hit
1522 event:0X0BC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP188 : (Group 188 pm_l2_ld_st) Number of run instructions completed.
1526 event:0X0BD0 counters:0 um:zero minimum:1000 name:PM_LARX_LSU_GRP189 : (Group 189 pm_stcx) Larx Finished
1527 event:0X0BD1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP189 : (Group 189 pm_stcx) The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
1528 event:0X0BD2 counters:2 um:zero minimum:1000 name:PM_STCX_CMPL_GRP189 : (Group 189 pm_stcx) Conditional stores with reservation completed
1529 event:0X0BD3 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP189 : (Group 189 pm_stcx) A stcx (stwcx or stdcx) failed
1530 event:0X0BD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP189 : (Group 189 pm_stcx) Number of run instructions completed.
1534 event:0X0BE0 counters:0 um:zero minimum:1000 name:PM_BTAC_HIT_GRP190 : (Group 190 pm_btac) BTAC Correct Prediction
1535 event:0X0BE1 counters:1 um:zero minimum:1000 name:PM_BTAC_MISS_GRP190 : (Group 190 pm_btac) BTAC Mispredicted
1536 event:0X0BE2 counters:2 um:zero minimum:1000 name:PM_STCX_CMPL_GRP190 : (Group 190 pm_btac) Conditional stores with reservation completed
1537 event:0X0BE3 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP190 : (Group 190 pm_btac) A stcx (stwcx or stdcx) failed
1538 event:0X0BE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP190 : (Group 190 pm_btac) Number of run instructions completed.
1542 event:0X0BF0 counters:0 um:zero minimum:1000 name:PM_BC_PLUS_8_CONV_GRP191 : (Group 191 pm_br_bc) BC+8 Converted
1543 event:0X0BF1 counters:1 um:zero minimum:1000 name:PM_BC_PLUS_8_RSLV_TAKEN_GRP191 : (Group 191 pm_br_bc) BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled
1546 event:0X0BF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP191 : (Group 191 pm_br_bc) Number of run instructions completed.
1550 event:0X0C00 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP192 : (Group 192 pm_inst_imc) Number of instructions resulting from the marked instructions expansion that completed.
1551 event:0X0C01 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP192 : (Group 192 pm_inst_imc) Number of PowerPC instructions successfully dispatched.
1552 event:0X0C02 counters:2 um:zero minimum:1000 name:PM_INST_IMC_MATCH_DISP_GRP192 : (Group 192 pm_inst_imc) IMC Matches dispatched
1554 event:0X0C04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP192 : (Group 192 pm_inst_imc) Number of run instructions completed.
1558 event:0X0C10 counters:0 um:zero minimum:1000 name:PM_L2_LDST_GRP193 : (Group 193 pm_l2_misc1) Data Load+Store Count
1559 event:0X0C11 counters:1 um:zero minimum:1000 name:PM_L2_LDST_MISS_GRP193 : (Group 193 pm_l2_misc1) Data Load+Store Miss
1560 event:0X0C12 counters:2 um:zero minimum:1000 name:PM_L2_INST_MISS_GRP193 : (Group 193 pm_l2_misc1) Instruction Load Misses
1561 event:0X0C13 counters:3 um:zero minimum:1000 name:PM_L2_DISP_ALL_GRP193 : (Group 193 pm_l2_misc1) All successful LD/ST dispatches for this thread(i+d)
1562 event:0X0C14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP193 : (Group 193 pm_l2_misc1) Number of run instructions completed.
1568 event:0X0C22 counters:2 um:zero minimum:1000 name:PM_L2_INST_GRP194 : (Group 194 pm_l2_misc2) Instruction Load Count
1569 event:0X0C23 counters:3 um:zero minimum:1000 name:PM_L2_DISP_ALL_GRP194 : (Group 194 pm_l2_misc2) All successful LD/ST dispatches for this thread(i+d)
1570 event:0X0C24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP194 : (Group 194 pm_l2_misc2) Number of run instructions completed.
1576 event:0X0C32 counters:2 um:zero minimum:1000 name:PM_L2_SYS_PUMP_GRP195 : (Group 195 pm_l2_misc3) RC req that was a global (aka system) pump attempt
1577 event:0X0C33 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP195 : (Group 195 pm_l2_misc3) Number of run instructions completed.
1578 event:0X0C34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP195 : (Group 195 pm_l2_misc3) Number of run instructions completed.
1584 event:0X0C42 counters:2 um:zero minimum:1000 name:PM_L2_SN_SX_I_DONE_GRP196 : (Group 196 pm_l2_misc4) SNP dispatched and went from Sx or Tx to Ix
1585 event:0X0C43 counters:3 um:zero minimum:1000 name:PM_L2_SN_M_WR_DONE_GRP196 : (Group 196 pm_l2_misc4) SNP dispatched for a write and was M
1586 event:0X0C44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP196 : (Group 196 pm_l2_misc4) Number of run instructions completed.
1592 event:0X0C52 counters:2 um:zero minimum:1000 name:PM_L2_NODE_PUMP_GRP197 : (Group 197 pm_l2_misc5) RC req that was a local (aka node) pump attempt
1593 event:0X0C53 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP197 : (Group 197 pm_l2_misc5) Number of run instructions completed.
1594 event:0X0C54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP197 : (Group 197 pm_l2_misc5) Number of run instructions completed.
1601 event:0X0C63 counters:3 um:zero minimum:1000 name:PM_L2_SN_M_RD_DONE_GRP198 : (Group 198 pm_l2_misc6) SNP dispatched for a read and was M
1602 event:0X0C64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP198 : (Group 198 pm_l2_misc6) Number of run instructions completed.
1606 event:0X0C70 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP199 : (Group 199 pm_ierat) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
1607 event:0X0C71 counters:1 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_16MPLUS_GRP199 : (Group 199 pm_ierat) large page 16M+
1608 event:0X0C72 counters:2 um:zero minimum:1000 name:PM_IERAT_WR_64K_GRP199 : (Group 199 pm_ierat) large page 64k
1610 event:0X0C74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP199 : (Group 199 pm_ierat) Number of run instructions completed.
1614 event:0X0C80 counters:0 um:zero minimum:1000 name:PM_DISP_CLB_HELD_GRP200 : (Group 200 pm_disp_clb) CLB Hold: Any Reason
1615 event:0X0C81 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_SB_GRP200 : (Group 200 pm_disp_clb) Dispatch/CLB Hold: Scoreboard
1618 event:0X0C84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP200 : (Group 200 pm_disp_clb) Number of run instructions completed.
1623 event:0X0C91 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP201 : (Group 201 pm_dpu) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
1624 event:0X0C92 counters:2 um:zero minimum:1000 name:PM_DISP_WT_GRP201 : (Group 201 pm_dpu) Dispatched Starved (not held, nothing to dispatch)
1626 event:0X0C94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP201 : (Group 201 pm_dpu) Number of run instructions completed.
1630 event:0X0CA0 counters:0 um:zero minimum:1000 name:PM_RUN_SPURR_GRP202 : (Group 202 pm_cpu_util) Run SPURR
1633 event:0X0CA3 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP202 : (Group 202 pm_cpu_util) The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads.
1634 event:0X0CA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP202 : (Group 202 pm_cpu_util) Number of run instructions completed.
1638 event:0X0CB0 counters:0 um:zero minimum:1000 name:PM_PMC4_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC4 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1639 event:0X0CB1 counters:1 um:zero minimum:1000 name:PM_PMC1_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC1 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1640 event:0X0CB2 counters:2 um:zero minimum:1000 name:PM_PMC2_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC2 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1641 event:0X0CB3 counters:3 um:zero minimum:1000 name:PM_PMC3_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC3 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1642 event:0X0CB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP203 : (Group 203 pm_overflow1) Number of run instructions completed.
1646 event:0X0CC0 counters:0 um:zero minimum:1000 name:PM_PMC5_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC5 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1647 event:0X0CC1 counters:1 um:zero minimum:1000 name:PM_PMC1_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC1 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1648 event:0X0CC2 counters:2 um:zero minimum:1000 name:PM_PMC6_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC6 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1649 event:0X0CC3 counters:3 um:zero minimum:1000 name:PM_PMC3_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC3 are counted.  This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
1650 event:0X0CC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP204 : (Group 204 pm_overflow2) Number of run instructions completed.
1654 event:0X0CD0 counters:0 um:zero minimum:1000 name:PM_PMC4_REWIND_GRP205 : (Group 205 pm_rewind) PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
1656 event:0X0CD2 counters:2 um:zero minimum:1000 name:PM_PMC2_REWIND_GRP205 : (Group 205 pm_rewind) PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
1658 event:0X0CD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP205 : (Group 205 pm_rewind) Number of run instructions completed.
1662 event:0X0CE0 counters:0 um:zero minimum:1000 name:PM_PMC2_SAVED_GRP206 : (Group 206 pm_saved) PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
1664 event:0X0CE2 counters:2 um:zero minimum:1000 name:PM_PMC4_SAVED_GRP206 : (Group 206 pm_saved) PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
1666 event:0X0CE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP206 : (Group 206 pm_saved) Number of run instructions completed.
1670 event:0X0CF0 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_TLBIE_GRP207 : (Group 207 pm_tlbie) Dispatch Flush: TLBIE
1671 event:0X0CF1 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_TLBIE_GRP207 : (Group 207 pm_tlbie) Dispatch Hold: Due to TLBIE
1672 event:0X0CF2 counters:2 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP207 : (Group 207 pm_tlbie) A tlbie was snooped from another processor.
1674 event:0X0CF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP207 : (Group 207 pm_tlbie) Number of run instructions completed.
1678 event:0X0D00 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP208 : (Group 208 pm_id_miss_erat_l1) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
1679 event:0X0D01 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP208 : (Group 208 pm_id_miss_erat_l1) An instruction fetch request missed the L1 cache.
1680 event:0X0D02 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP208 : (Group 208 pm_id_miss_erat_l1) A store missed the dcache.  Combined Unit 0 + 1.
1681 event:0X0D03 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP208 : (Group 208 pm_id_miss_erat_l1) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
1682 event:0X0D04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP208 : (Group 208 pm_id_miss_erat_l1) Number of run instructions completed.
1687 event:0X0D11 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) Total D-ERAT Misses.  Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.  Combined Unit 0 + 1.
1688 event:0X0D12 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) Data TLB misses, all page sizes.
1689 event:0X0D13 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) A TLB miss for an Instruction Fetch has occurred
1690 event:0X0D14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP209 : (Group 209 pm_id_miss_erat_tlab) Number of run instructions completed.
1694 event:0X0D20 counters:0 um:zero minimum:1000 name:PM_ANY_THRD_RUN_CYC_GRP210 : (Group 210 pm_compat_utilization1) One of threads in run_cycles
1697 event:0X0D23 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP210 : (Group 210 pm_compat_utilization1) The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads.
1698 event:0X0D24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP210 : (Group 210 pm_compat_utilization1) Number of run instructions completed.
1702 event:0X0D30 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP211 : (Group 211 pm_compat_utilization2) A floating point operation has completed
1705 event:0X0D33 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP211 : (Group 211 pm_compat_utilization2) Number of run instructions completed.
1706 event:0X0D34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP211 : (Group 211 pm_compat_utilization2) Number of run instructions completed.
1710 event:0X0D40 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
1712 event:0X0D42 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Number of PowerPC instructions successfully dispatched.
1713 event:0X0D43 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
1714 event:0X0D44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Number of run instructions completed.
1719 event:0X0D51 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Store requests sent to the nest.
1720 event:0X0D52 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) A store missed the dcache.  Combined Unit 0 + 1.
1721 event:0X0D53 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
1722 event:0X0D54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Number of run instructions completed.
1727 event:0X0D61 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP214 : (Group 214 pm_compat_l1_cache_load) The processor's Data Cache was reloaded but not from the local L2.
1728 event:0X0D62 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP214 : (Group 214 pm_compat_l1_cache_load) The data source information is valid,the data cache has been reloaded.  Prior to POWER5+ this included data cache reloads due to prefetch activity.  With POWER5+ this now only includes reloads due to demand loads.
1729 event:0X0D63 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP214 : (Group 214 pm_compat_l1_cache_load) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
1730 event:0X0D64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP214 : (Group 214 pm_compat_l1_cache_load) Number of run instructions completed.
1734 event:0X0D70 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
1735 event:0X0D71 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) An instruction fetch request missed the L1 cache.
1737 event:0X0D73 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) A TLB miss for an Instruction Fetch has occurred
1738 event:0X0D74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP215 : (Group 215 pm_compat_instruction_directory) Number of run instructions completed.
1742 event:0X0D80 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
1743 event:0X0D81 counters:1 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
1744 event:0X0D82 counters:2 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
1745 event:0X0D83 counters:3 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
1746 event:0X0D84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP216 : (Group 216 pm_compat_suspend) Number of run instructions completed.
1751 event:0X0D91 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP217 : (Group 217 pm_compat_misc_events1) An interrupt due to an external exception occurred
1752 event:0X0D92 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP217 : (Group 217 pm_compat_misc_events1) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
1754 event:0X0D94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP217 : (Group 217 pm_compat_misc_events1) Number of run instructions completed.
1758 event:0X0DA0 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP218 : (Group 218 pm_compat_misc_events2) Number of instructions resulting from the marked instructions expansion that completed.
1759 event:0X0DA1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP218 : (Group 218 pm_compat_misc_events2) Number of PowerPC instructions successfully dispatched.
1760 event:0X0DA2 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP218 : (Group 218 pm_compat_misc_events2) Instructions completed by this thread when both threads had their run latches set.
1761 event:0X0DA3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP218 : (Group 218 pm_compat_misc_events2) Flushes occurred including LSU and Branch flushes.
1762 event:0X0DA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP218 : (Group 218 pm_compat_misc_events2) Number of run instructions completed.
1766 event:0X0DB0 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP219 : (Group 219 pm_compat_misc_events3) Cycles when the Global Completion Table has no slots from this thread.
1767 event:0X0DB1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP219 : (Group 219 pm_compat_misc_events3) Number of PowerPC instructions successfully dispatched.
1769 event:0X0DB3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP219 : (Group 219 pm_compat_misc_events3) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
1770 event:0X0DB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP219 : (Group 219 pm_compat_misc_events3) Number of run instructions completed.
1774 event:0X0DC0 counters:0 um:zero minimum:1000 name:PM_MRK_BR_TAKEN_GRP220 : (Group 220 pm_mrk_br) A marked branch was taken
1775 event:0X0DC1 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP220 : (Group 220 pm_mrk_br) Marked L1 D cache load misses
1776 event:0X0DC2 counters:2 um:zero minimum:1000 name:PM_MRK_BR_MPRED_GRP220 : (Group 220 pm_mrk_br) A marked branch was mispredicted
1778 event:0X0DC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP220 : (Group 220 pm_mrk_br) Number of run instructions completed.
1782 event:0X0DD0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DMEM_GRP221 : (Group 221 pm_mrk_dsource1) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.
1783 event:0X0DD1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DMEM_CYC_GRP221 : (Group 221 pm_mrk_dsource1) Marked ld latency Data Source 1110 (Distant Memory)
1784 event:0X0DD2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_MOD_GRP221 : (Group 221 pm_mrk_dsource1) Marked data loaded from another L2 on same chip modified
1785 event:0X0DD3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_MOD_CYC_GRP221 : (Group 221 pm_mrk_dsource1) Marked ld latency Data source 0101 (L2.1 M same chip)
1786 event:0X0DD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP221 : (Group 221 pm_mrk_dsource1) Number of run instructions completed.
1790 event:0X0DE0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP222 : (Group 222 pm_mrk_dsource2) The processor's Data Cache was reloaded from the local L3 due to a marked load.
1791 event:0X0DE1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP222 : (Group 222 pm_mrk_dsource2) Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.
1792 event:0X0DE2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP222 : (Group 222 pm_mrk_dsource2) The processor?s Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.
1793 event:0X0DE3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP222 : (Group 222 pm_mrk_dsource2) Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.
1794 event:0X0DE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP222 : (Group 222 pm_mrk_dsource2) Number of run instructions completed.
1798 event:0X0DF0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_MOD_GRP223 : (Group 223 pm_mrk_dsource3) Marked data loaded from another L3 on same chip modified
1799 event:0X0DF1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_SHR_CYC_GRP223 : (Group 223 pm_mrk_dsource3) Marked load latency Data source 0100 (L2.1 S)
1800 event:0X0DF2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_SHR_GRP223 : (Group 223 pm_mrk_dsource3) Marked data loaded from another L2 on same chip shared
1801 event:0X0DF3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_MOD_CYC_GRP223 : (Group 223 pm_mrk_dsource3) Marked ld latency Data source 0111  (L3.1 M same chip)
1802 event:0X0DF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP223 : (Group 223 pm_mrk_dsource3) Number of run instructions completed.
1806 event:0X0E00 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP224 : (Group 224 pm_mrk_dsource4) The processor's Data Cache was reloaded from the local L2 due to a marked load.
1807 event:0X0E01 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP224 : (Group 224 pm_mrk_dsource4) Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.
1808 event:0X0E02 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP224 : (Group 224 pm_mrk_dsource4) The processor?s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
1809 event:0X0E03 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP224 : (Group 224 pm_mrk_dsource4) The processor?s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
1810 event:0X0E04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP224 : (Group 224 pm_mrk_dsource4) Number of run instructions completed.
1814 event:0X0E10 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_GRP225 : (Group 225 pm_mrk_dsource5) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a remote module due to a marked load.
1815 event:0X0E11 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_SHR_CYC_GRP225 : (Group 225 pm_mrk_dsource5) Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)
1816 event:0X0E12 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_SHR_GRP225 : (Group 225 pm_mrk_dsource5) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.
1817 event:0X0E13 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_CYC_GRP225 : (Group 225 pm_mrk_dsource5) Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)
1818 event:0X0E14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP225 : (Group 225 pm_mrk_dsource5) Number of run instructions completed.
1822 event:0X0E20 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_GRP226 : (Group 226 pm_mrk_dsource6) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load
1823 event:0X0E21 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_CYC_GRP226 : (Group 226 pm_mrk_dsource6) Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)
1824 event:0X0E22 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP226 : (Group 226 pm_mrk_dsource6) The processor?s Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.
1825 event:0X0E23 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP226 : (Group 226 pm_mrk_dsource6) Cycles a marked load waited for data from this level of the storage system.  Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache.  To calculate average latency divide this count by the number of marked misses to the same level.
1826 event:0X0E24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP226 : (Group 226 pm_mrk_dsource6) Number of run instructions completed.
1830 event:0X0E30 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_SHR_GRP227 : (Group 227 pm_mrk_dsource7) Marked data loaded from another L3 on same chip shared
1831 event:0X0E31 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_SHR_CYC_GRP227 : (Group 227 pm_mrk_dsource7) Marked load latency Data source 0110 (L3.1 S)
1832 event:0X0E32 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP227 : (Group 227 pm_mrk_dsource7) One of the execution units finished a marked instruction.  Instructions that finish may not necessary complete
1833 event:0X0E33 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP227 : (Group 227 pm_mrk_dsource7) DL1 was reloaded from beyond L2 due to a marked demand load.
1834 event:0X0E34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP227 : (Group 227 pm_mrk_dsource7) Number of run instructions completed.
1838 event:0X0E40 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP228 : (Group 228 pm_mrk_dsource8) Marked Load exposed Miss (use edge detect to count #)
1839 event:0X0E41 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3MISS_GRP228 : (Group 228 pm_mrk_dsource8) DL1 was reloaded from beyond L3 due to a marked load.
1840 event:0X0E42 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_MOD_GRP228 : (Group 228 pm_mrk_dsource8) The processor's Data Cache was reloaded with modified (M) data from an L2  or L3 on a distant module due to a marked load.
1841 event:0X0E43 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_MOD_CYC_GRP228 : (Group 228 pm_mrk_dsource8) Marked ld latency Data source 1011  (L2.75/L3.75 M different 4 chip node)
1842 event:0X0E44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP228 : (Group 228 pm_mrk_dsource8) Number of run instructions completed.
1846 event:0X0E50 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP229 : (Group 229 pm_mrk_lsu_flush1) A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)
1847 event:0X0E51 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP229 : (Group 229 pm_mrk_lsu_flush1) A marked store was flushed because it was unaligned
1850 event:0X0E54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP229 : (Group 229 pm_mrk_lsu_flush1) Number of run instructions completed.
1856 1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP230 : (Group 230 pm_mrk_lsu_flush2) Load Hit Load or Store Hit Load flush.  A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
1857 event:0X0E63 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP230 : (Group 230 pm_mrk_lsu_flush2) Load Hit Store flush.  A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group.  If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding.  If the load and store are in the same group the load must be flushed to separate the two instructions.
1858 event:0X0E64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP230 : (Group 230 pm_mrk_lsu_flush2) Number of run instructions completed.
1862 event:0X0E70 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP231 : (Group 231 pm_mrk_rejects) The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully
1863 event:0X0E71 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_GRP231 : (Group 231 pm_mrk_rejects) Marked flush initiated by LSU
1865 event:0X0E73 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_GRP231 : (Group 231 pm_mrk_rejects) LSU marked reject (up to 2 per cycle)
1866 event:0X0E74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP231 : (Group 231 pm_mrk_rejects) Number of run instructions completed.
1870 event:0X0E80 counters:0 um:zero minimum:1000 name:PM_MRK_INST_ISSUED_GRP232 : (Group 232 pm_mrk_inst) A marked instruction was issued to an execution unit.
1871 event:0X0E81 counters:1 um:zero minimum:1000 name:PM_MRK_INST_DISP_GRP232 : (Group 232 pm_mrk_inst) A marked instruction was dispatched
1872 event:0X0E82 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP232 : (Group 232 pm_mrk_inst) One of the execution units finished a marked instruction.  Instructions that finish may not necessary complete
1874 event:0X0E84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP232 : (Group 232 pm_mrk_inst) Number of run instructions completed.
1878 event:0X0E90 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP233 : (Group 233 pm_mrk_st) A sampled store has completed (data home)
1879 event:0X0E91 counters:1 um:zero minimum:1000 name:PM_MRK_ST_NEST_GRP233 : (Group 233 pm_mrk_st) A sampled store has been sent to the memory subsystem
1880 event:0X0E92 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP233 : (Group 233 pm_mrk_st) A marked store previously sent to the memory subsystem completed (data home) after requiring intervention
1882 event:0X0E94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP233 : (Group 233 pm_mrk_st) Number of run instructions completed.
1887 event:0X0EA1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1888 event:0X0EA2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1889 event:0X0EA3 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1890 event:0X0EA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Number of run instructions completed.
1894 event:0X0EB0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1895 event:0X0EB1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1896 event:0X0EB2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
1898 event:0X0EB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Number of run instructions completed.
1903 event:0X0EC1 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
1904 event:0X0EC2 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16M_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
1905 event:0X0EC3 counters:3 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16G_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
1906 event:0X0EC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP236 : (Group 236 pm_mrk_derat_miss1) Number of run instructions completed.
1910 event:0X0ED0 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_4K_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
1911 event:0X0ED1 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
1912 event:0X0ED2 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16M_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
1914 event:0X0ED4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP237 : (Group 237 pm_mrk_derat_miss2) Number of run instructions completed.
1918 event:0X0EE0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_EXPOSED_CYC_GRP238 : (Group 238 pm_mrk_misc_miss) Marked Load exposed Miss
1920 event:0X0EE2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_DERAT_MISS_GRP238 : (Group 238 pm_mrk_misc_miss) Marked DERAT Miss
1921 event:0X0EE3 counters:3 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_CYC_GRP238 : (Group 238 pm_mrk_misc_miss) L1 data load miss cycles
1922 event:0X0EE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP238 : (Group 238 pm_mrk_misc_miss) Number of run instructions completed.
1927 event:0X0EF1 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DMEM_GRP239 : (Group 239 pm_mrk_pteg1) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
1928 event:0X0EF2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_MOD_GRP239 : (Group 239 pm_mrk_pteg1) Marked PTEG loaded from another L2 on same chip modified
1929 event:0X0EF3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_SHR_GRP239 : (Group 239 pm_mrk_pteg1) Marked PTEG loaded from another L2 on same chip shared
1930 event:0X0EF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP239 : (Group 239 pm_mrk_pteg1) Number of run instructions completed.
1934 event:0X0F00 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.
1935 event:0X0F01 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_SHR_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
1936 event:0X0F02 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RMEM_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
1938 event:0X0F04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP240 : (Group 240 pm_mrk_pteg2) Number of run instructions completed.
1943 event:0X0F11 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L31_SHR_GRP241 : (Group 241 pm_mrk_pteg3) Marked PTEG loaded from another L3 on same chip shared
1944 event:0X0F12 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_MOD_GRP241 : (Group 241 pm_mrk_pteg3) Marked PTEG loaded from another L2 on same chip modified
1945 event:0X0F13 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_MOD_GRP241 : (Group 241 pm_mrk_pteg3) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2  or L3 on a distant module due to a marked load or store.
1946 event:0X0F14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP241 : (Group 241 pm_mrk_pteg3) Number of run instructions completed.
1950 event:0X0F20 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L31_MOD_GRP242 : (Group 242 pm_mrk_pteg4) Marked PTEG loaded from another L3 on same chip modified
1951 event:0X0F21 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3_GRP242 : (Group 242 pm_mrk_pteg4) A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.
1953 event:0X0F23 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2MISS_GRP242 : (Group 242 pm_mrk_pteg4) A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.
1954 event:0X0F24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP242 : (Group 242 pm_mrk_pteg4) Number of run instructions completed.
1958 1000 name:PM_MRK_PTEG_FROM_RL2L3_MOD_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.
1959 event:0X0F31 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3MISS_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store
1961 event:0X0F33 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_LMEM_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.
1962 event:0X0F34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP243 : (Group 243 pm_mrk_pteg5) Number of run instructions completed.
1966 event:0X0F40 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP244 : (Group 244 pm_mrk_misc1) A marked stcx (stwcx or stdcx) failed
1968 event:0X0F42 counters:2 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP244 : (Group 244 pm_mrk_misc1) The Instruction Fetch Unit finished a marked instruction.
1969 event:0X0F43 counters:3 um:zero minimum:1000 name:PM_MRK_INST_TIMEO_GRP244 : (Group 244 pm_mrk_misc1) The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.
1970 event:0X0F44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP244 : (Group 244 pm_mrk_misc1) Number of run instructions completed.
1975 event:0X0F51 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP245 : (Group 245 pm_mrk_misc2) One of the Fixed Point Units finished a marked instruction.  Instructions that finish may not necessary complete.
1976 event:0X0F52 counters:2 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP245 : (Group 245 pm_mrk_misc2) The Instruction Fetch Unit finished a marked instruction.
1977 event:0X0F53 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP245 : (Group 245 pm_mrk_misc2) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
1978 event:0X0F54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP245 : (Group 245 pm_mrk_misc2) Number of run instructions completed.
1983 event:0X0F61 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP246 : (Group 246 pm_mrk_misc3) The branch unit finished a marked instruction. Instructions that finish may not necessary complete.
1984 event:0X0F62 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_PARTIAL_CDF_GRP246 : (Group 246 pm_mrk_misc3) A partial cacheline was returned from the L3 for a marked load
1985 event:0X0F63 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP246 : (Group 246 pm_mrk_misc3) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
1986 event:0X0F64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP246 : (Group 246 pm_mrk_misc3) Number of run instructions completed.
1990 event:0X0F70 counters:0 um:zero minimum:1000 name:PM_MRK_FIN_STALL_CYC_GRP247 : (Group 247 pm_mrk_misc4) Marked instruction Finish Stall cycles (marked finish after NTC)
1992 event:0X0F72 counters:2 um:zero minimum:1000 name:PM_MRK_VSU_FIN_GRP247 : (Group 247 pm_mrk_misc4) vsu (fpu) marked  instr finish
1993 event:0X0F73 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP247 : (Group 247 pm_mrk_misc4) A group containing a marked (sampled) instruction experienced an instruction cache miss.
1994 event:0X0F74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP247 : (Group 247 pm_mrk_misc4) Number of run instructions completed.
1998 event:0X0F80 counters:0 um:zero minimum:1000 name:PM_MRK_FIN_STALL_CYC_COUNT_GRP248 : (Group 248 pm_mrk_misc5) Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)
1999 event:0X0F81 counters:1 um:zero minimum:1000 name:PM_MRK_DFU_FIN_GRP248 : (Group 248 pm_mrk_misc5) The Decimal Floating Point Unit finished a marked instruction.
2000 event:0X0F82 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_COUNT_GRP248 : (Group 248 pm_mrk_misc5) Marked Group Completion Stall cycles (use edge detect to count #)
2002 event:0X0F84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP248 : (Group 248 pm_mrk_misc5) Number of run instructions completed.
2006 event:0X0F90 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_CYC_GRP249 : (Group 249 pm_mrk_misc6) cycles IDU marked instruction before dispatch
2009 event:0X0F93 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP249 : (Group 249 pm_mrk_misc6) A group containing a sampled instruction completed.  Microcoded instructions that span multiple groups will generate this event once per group.
2010 event:0X0F94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP249 : (Group 249 pm_mrk_misc6) Number of run instructions completed.
2014 event:0X0FA0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP250 : (Group 250 pm_mrk_misc7) The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully
2016 event:0X0FA2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ERAT_MISS_GRP250 : (Group 250 pm_mrk_misc7) LSU marked reject due to ERAT (up to 2 per cycle)
2017 event:0X0FA3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_GRP250 : (Group 250 pm_mrk_misc7) LSU marked reject (up to 2 per cycle)
2018 event:0X0FA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP250 : (Group 250 pm_mrk_misc7) Number of run instructions completed.
2025 event:0X0FB3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP251 : (Group 251 pm_mrk_misc8) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
2026 event:0X0FB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP251 : (Group 251 pm_mrk_misc8) Number of run instructions completed.
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